pll
Here are 76 public repositories matching this topic...
This repository presents design of on-chip clock multiplier(8X PLL) using open source EDA tool OSU 180nm technology node
-
Updated
Oct 20, 2021
This project implements a bit 10000 error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.
-
Updated
Jun 2, 2022 - Verilog
SAA1057 Stereo PLL Controller
-
Updated
Mar 5, 2025 - Assembly
Design of Phase locked loop for 2.4 GHz frequency in 180nm Technology
-
Updated
Apr 28, 2025 - AGS Script
8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
-
Updated
Jul 21, 2022
Modified version of Si5351_OLED_DFS for simple CW TX use or DC receiver.
-
Updated
Mar 28, 2019 - C++
Rubik's cube solver using CFOP
-
Updated
Dec 5, 2021 - Python
Train your PLL skills on Rubik's cube with this groovy script
-
Updated
Apr 26, 2018 - Groovy
A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).
-
Updated
Nov 20, 2024 - Scala
Firmware (Sketch) for Arduino MEGA DDS (Direct Digital Synthesis) Analog Devices AD9915 Arduino Shield by GRA & AFCH
-
Updated
Feb 27, 2023
Design of Phase-Locked-Loop using 45nm technology on Cadence Virtuoso tool
-
Updated
Oct 30, 2025
Improve this page
Add a description, image, and links to the pll topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the pll topic, visit your repo's landing page and select "manage topics."