pll
Here are 76 public repositories matching this topic...
This repository presents design of on-chip clock multiplier(8X PLL) using open source EDA tool OSU 180nm technology node
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Oct 20, 2021
This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.
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Jun 2, 2022 - Verilog
Design of Phase locked loop for 2.4 GHz frequency in 180nm Technology
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Apr 28, 2025 - AGS Script
Train your PLL skills on Rubik's cube with this groovy script
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Apr 26, 2018 - Groovy
Firmware (Sketch) for Arduino MEGA DDS (Direct Digital Synthesis) Analog Devices AD9915 Arduino Shield by GRA & AFCH
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Feb 27, 2023
Design of Phase-Locked-Loop using 45nm technology on Cadence Virtuoso tool
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Oct 30, 2025
A Simulink Model of Dynamic Mode AFM
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Mar 1, 2024 - MATLAB
TSA5511 PLL Controller for Arduino
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Oct 28, 2025 - C++
Compute Pseudo-Log-Likelihood (PLL) and PPPL for protein sequences using ESM2 models
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Jul 17, 2025 - Python
This project provides a simple and well-documented MATLAB implementation of a Phase-Locked Loop (PLL), developed as part of a 5th semester mini project. The final version focuses on clarity, structure, and ease of understanding.
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Jan 5, 2025 - MATLAB
Self consistent model based filter design for 3-phase PLLs.
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Jan 4, 2018 - Makefile
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Jul 25, 2021 - Assembly
Generating PLL configuration parameters
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Feb 9, 2025 - Rust
笔电间通过3.5mm交叉线缆或扬声器/麦克风通信 PC-PC communication via 3.5mm TRRS2TRRS(crossed) cable or speakers/microphones
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Nov 29, 2025 - C++
A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier
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May 31, 2022 - Verilog
Alternative version of the MTS module (https://github.com/TU-Darmstadt-APQ/MTS_module) for 80 MHz and 200 MHz AOMs.
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Dec 17, 2023
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