8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
FOC driver library written in Rust
"SguanESC无刷电调库"采用三相分压电阻电压检测方案，为BLDC电机提供强大的无感控制方案。该库内部集成了六步换相逻辑与无刷电机过零检测功能，并通过电机状态机实现对BLDC电机的精确控制与灵活调节。库代码采用纯逻辑实现，支持用户移植到任何C语言开发的mcu中 ≡Σ(((つ•̀ω•́)つ
iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter
Single-Phase PLL / Second-Order Generalized Integrators Phase Lock Loop
8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
Sensorless FOC (PLL estimator) of AC induction motor with field weakening
This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.
verilog modules
This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.
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