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dma

Here are 15 public repositories matching this topic...

open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

linux fpga zynq hls hardware vhdl rtl verilog xilinx sdr wi-fi analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 mac80211

Updated Sep 23, 2025
Verilog

rtl8125_emulation

pa1n-dev / rtl8125_emulation

Guilde how to create custom DMA firmware.

fpga guide emulation bypass dma pcileech battle-eye dma-attack eac-bypass-tool pcileech-fpga

Updated Aug 27, 2025
Verilog

shalan / MS_DMAC_AHBL

A Direct Memory Access Controller (DMAC) with AHB-lite bus interface

asic fpga verilog dma dmac ahb-lite

Updated Oct 6, 2024
Verilog

12i192i1043 / pcileech-cmedia-cmi8738

C-Media CMI8738/PCI-SX PCIe sound card emulation for PCILeech DMA boards (Artix-7)

fpga vivado systemverilog hardware-emulation dma pcie artix-7 pcileech cmi8738

Updated Jul 20, 2026
Verilog

AhmedSobhy01 / convolution-accelerator

Hardware accelerator for 2D convolution using an 8×8 weight-stationary systolic array with split-kernel support, dual-port SRAM architecture, and DMA-based streaming

fpga verilog sram convolution vlsi dma digital-design systolic-arrays rtl-design hardware-accelerator systolic-array

Updated Jul 23, 2026
Verilog

ichigo-6301 / slvc-dma-open

512-bit multi-channel DMA for shared links with channel-aware admission, hybrid buffering, CDC backends and FPGA/ASIC evidence.

asic fpga verilog multi-channel cdc dma primetime axi-stream axi4 openroad

Updated Aug 17, 2026
Verilog

mjh-design / AXI_DMA

一个基于AXI的DMA

ip dma axi

Updated Nov 18, 2022
Verilog

noritan / Design363

FIFO and DMA combination study - "CY8C5888AXI-LP096" on "FreeSoC2"

uart datapath fifo dma psoc5lp cy8ckit-059

Updated Jun 2, 2020
Verilog

shreyanshsharma639 / DMA-Memory-Subsystem

A high performance DMA subsystem using AXI4 Full protocols and a custom 16 bank eDRAM architecture. Designed for maximum throughput and minimal leakage, it features predictive bank wakeup logic and deterministic timing closure at 100MHz.

fpga rtl vivado dma system-design vlsi-design edram testbench-verification

Updated Mar 11, 2026
Verilog

NetVar1337 / pcileech-fpga

FPGA modules for PCILeech DMA attack software

fpga hardware verilog dma security-research pcileech

Updated Jun 28, 2026
Verilog

bvbhavana1 / Implementation-and-RTL-Design-of-DMA-Controller-using-Verilog-in-Xilinx-ISE-14.7

Designed FSM-based DMA controller in Verilog for efficient memory transfer, reducing CPU dependency and improving system throughput

rtl verilog dma xilinx-ise

Updated Aug 22, 2026
Verilog

mjh-design / DMA-S2MM-and-MM2S

Build an open source, extremely simple DMA.

ip dma axi

Updated Feb 17, 2019
Verilog

Saad1507 / amba-dma-controller

AXI-based DMA engine (memory-to-memory transfer) in Verilog

verilog dma amba rtl-design direct-memory-access soc-interconnect

Updated Aug 23, 2026
Verilog

Rice-MECE-Capstone-Projects / Hydra

Data movement hardware accelerator for autonomous data transformation in the Wally RISC-V SoC.

hardware-acceleration risc-v dma

Updated May 5, 2026
Verilog

pocper / NYCU-SoC-Project-2023

交大電子碩系統晶片設計期末專題第七組

verilog dma arbiter vexriscv

Updated May 8, 2026
Verilog

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