pipelining

Here are 7 public repositories matching this topic...

Awais-Asghar / 5-Stage-Pipelined-RISC-V-Processor-on-FPGA

A 5-Stage Pipelined RISC-V Processor designed and implemented on FPGA (Artix-7 Nexys A7). Supports RV32I instructions set (R, I, S, B, U, J types) with ALU, control unit, hazard detection, forwarding, and pipeline registers. Verified through simulation and hardware testing with optimized timing and 4× performance gain.

fpga processor systemverilog pipelining computer-architecture hazard-detection risc-v system-design riscv32 datapath-design pipelined-processor control-logic

Updated Oct 13, 2025
SystemVerilog

panoskoutris / fp-multiplier

Star

Pipelined IEEE-754 single-precision floating-point multiplier in SystemVerilog with full verification.

simulation multiplication verification rtl floating-point ieee-754 pipelining computer-architecture hdl questasim system-verilog digital-design sva intel-fpga hardware-design

Updated Aug 17, 2025
SystemVerilog

f-picciau / RV32I-5Stage-CPU-Design

Star

A 32-bit RISC-V processor (RV32I) with a 5-stage pipeline, written in SystemVerilog.

fpga vivado systemverilog pipelining risc-v cpu-architecture rtl-design

Updated Aug 21, 2026
SystemVerilog

sainithya-web / Pipelined-8bit-ALU-SystemVerilog

Star

A 2-stage pipelined ALU with an automated self-checking testbench.

verification digital-logic systemverilog pipelining vlsi rtl-design

Updated Feb 11, 2026
SystemVerilog

Rajeshwar-Reddy-Vemula / MIPS-5-Stage-Pipeline-Simulator

Star

MIPS Simulator with three following modes: ***A. Functional simulator *** B. No pipeline forwarding ***C. Pipeline forwarding

forwarding pipelining hazard-handling

Updated Feb 4, 2026
SystemVerilog

SrinnathK / KalmanFilter

Star

Kalman Filter HDL Implementation

pipelining folding kalmanfilter

Updated Apr 16, 2026
SystemVerilog

jfmedina05 / fpga-digital-design-accelerators

Star

FPGA hardware acceleration projects using SystemVerilog, AXI, DMA, C drivers, pipelining, and parallel compute architectures.

python c fpga parallel-computing embedded-systems vivado systemverilog pipelining pynq hardware-acceleration dma digital-design axi axi-stream axi4-lite 3BF3 memory-mapped-io hardware-software-co-design

Updated Jun 30, 2026
SystemVerilog

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