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Over 1% magnetoresistance ratio at room temperature in non-degenerate silicon-based lateral spin valves
Authors:
H. Koike,
S. Lee,
R. Ohshima,
E. Shigematsu,
M. Goto,
S. Miwa,
Y. Suzuki,
T. Sasaki,
Y. Ando,
M. Shiraishi
Abstract:
To augment the magnetoresistance (MR) ratio of n-type non-degenerate Si-based lateral spin valves (Si-LSVs), we modify the doping profile in the Si layer and introduce a larger local strain into the Si channel by changing a capping insulator. The highest MR ratio of 1.4% is achieved in the Si-LSVs through these improvements, with significant roles played by a reduction in the resistance-area produ…
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To augment the magnetoresistance (MR) ratio of n-type non-degenerate Si-based lateral spin valves (Si-LSVs), we modify the doping profile in the Si layer and introduce a larger local strain into the Si channel by changing a capping insulator. The highest MR ratio of 1.4% is achieved in the Si-LSVs through these improvements, with significant roles played by a reduction in the resistance-area product of the ferromagnetic contacts and an enhancement of the momentum relaxation time in the Si channel.
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Submitted 31 August, 2020;
originally announced August 2020.
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Investigation of gating effect in Si spin MOSFET
Authors:
Soobeom Lee,
Fabien Rortais,
Ryo Ohshima,
Yuichiro Ando,
Minori Goto,
Shinji Miwa,
Yoshishige Suzuki,
Hayato Koike,
Masashi Shiraishi
Abstract:
A gate voltage application in a Si-based spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) modulates spin accumulation voltages, where both electrical conductivity and drift velocity are modified while keeping constant electric current. An unprecedented reduction in the spin accumulation voltages in a Si spin MOSFET under negative gate voltage applications is observed in a high…
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A gate voltage application in a Si-based spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) modulates spin accumulation voltages, where both electrical conductivity and drift velocity are modified while keeping constant electric current. An unprecedented reduction in the spin accumulation voltages in a Si spin MOSFET under negative gate voltage applications is observed in a high electric bias current regime. To support our claim, the electric bias current dependence of the spin accumulation voltage under the gate voltage applications is investigated in detail and compared to a spin drift diffusion model including the conductance mismatch effect. We proved that the drastic decrease of the mobility and spin lifetime in the Si channel is due to the optical phonon emission at the high electric bias current, which consequently reduced the spin accumulation voltage.
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Submitted 28 October, 2019;
originally announced October 2019.
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Gate-tunable spin exclusive or operation in a silicon-based spin device at room temperature
Authors:
R. Ishihara,
Y. Ando,
S. Lee,
M. Goto,
S. Miwa,
Y. Suzuki,
H. Koike,
M. Shiraishi
Abstract:
Room temperature operation of a spin exclusive or (XOR) gate was demonstrated in lateral spin valve devices with nondegenerate silicon (Si) channels. The spin XOR gate is a fundamental part of the magnetic logic gate (MLG) that enables reconfigurable and nonvolatile NAND or OR operation in one device. The device for the spin XOR gate consists of three iron (Fe)/cobalt (Co)/magnesium oxide (MgO) el…
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Room temperature operation of a spin exclusive or (XOR) gate was demonstrated in lateral spin valve devices with nondegenerate silicon (Si) channels. The spin XOR gate is a fundamental part of the magnetic logic gate (MLG) that enables reconfigurable and nonvolatile NAND or OR operation in one device. The device for the spin XOR gate consists of three iron (Fe)/cobalt (Co)/magnesium oxide (MgO) electrodes, i.e., two input and one output electrodes. Spins are injected into the Si channel from the input electrodes whose spin angular momentum corresponds to the binary input 1 or 0. The spin drift effect is controlled by a lateral electric field in the Si channel to adjust the spin accumulation voltages under two different parallel configurations, corresponding to (1, 1) and (0, 0), so that they exhibit the same value. As a result, the spin accumulation voltage detected by the output electrode exhibits three different voltages, represented by an XOR gate. The one-dimensional spin drift-diffusion model clearly explains the obtained XOR behavior. Charge current detection of the spin XOR gate is also demonstrated. The detected charge current has a maximum of 0.94 nA, the highest value in spin XOR gates reported thus far. Furthermore, gate voltage modulation of the spin XOR gate is also demonstrated, which enables operation of multiple MLG devices.
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Submitted 13 September, 2019;
originally announced September 2019.
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Quantitative and systematic analysis of bias dependence of spin accumulation voltage in a non-degenerate Si spin valve
Authors:
Soobeom Lee,
Fabien Rortais,
Ryo Ohshima,
Yuichiro Ando,
Shinji Miwa,
Yoshishige Suzuki,
Hayato Koike,
Masashi Shiraishi
Abstract:
Spin accumulation voltages in a non-degenerate Si spin valve are discussed quantitatively as a function of electric bias current using systematic experiments and model calculations. As an open question in semiconductor spintronics, the origin of the deviation of spin accumulation voltages measured experimentally in a non-degenerate Si spin valve is clarified from that obtained by model calculation…
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Spin accumulation voltages in a non-degenerate Si spin valve are discussed quantitatively as a function of electric bias current using systematic experiments and model calculations. As an open question in semiconductor spintronics, the origin of the deviation of spin accumulation voltages measured experimentally in a non-degenerate Si spin valve is clarified from that obtained by model calculation using the spin drift diffusion equation including the effect of the spin-dependent interfacial resistance of tunneling barriers. Unlike the case of metallic spin valves, the bias dependence of the resistance-area product for a ferromagnet/MgO/Si interface, resulting in the reappearance of the conductance mismatch, plays a central role to induce the deviation.
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Submitted 16 October, 2018;
originally announced October 2018.
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Toward Practical-Scale Quantum Annealing Machine for Prime Factoring
Authors:
Masaaki Maezawa,
Go Fujii,
Mutsuo Hidaka,
Kentaro Imafuku,
Katsuya Kikuchi,
Hanpei Koike,
Kazumasa Makise,
Shuichi Nagasawa,
Hiroshi Nakagawa,
Masahiro Ukibe,
Shiro Kawabata
Abstract:
We propose a prime factorizer operated in a framework of quantum annealing (QA). The idea is inverse operation of a multiplier implemented with QA-based Boolean logic circuits. We designed the QA machine on an application-specific-annealing-computing architecture which efficiently increases available hardware budgets at the cost of restricted functionality. The invertible operation of QA logic gat…
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We propose a prime factorizer operated in a framework of quantum annealing (QA). The idea is inverse operation of a multiplier implemented with QA-based Boolean logic circuits. We designed the QA machine on an application-specific-annealing-computing architecture which efficiently increases available hardware budgets at the cost of restricted functionality. The invertible operation of QA logic gates consisting of superconducting flux qubits was confirmed by circuit simulation with classical noise sources. The circuits were implemented and fabricated by using superconducting integrated circuit technologies with Nb/AlOx/Nb Josephson junctions. We also propose a 2.5Dimensional packaging scheme of a qubit-chip/interpose /package-substrate structure for realizing practically large-scale QA systems.
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Submitted 5 September, 2018;
originally announced September 2018.
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Design of Quantum Annealing Machine for Prime Factoring
Authors:
M. Maezawa,
K. Imafuku,
M. Hidaka,
H. Koike,
S. Kawabata
Abstract:
We propose a prime factoring machine operated in a frame work of quantum annealing (QA). The idea is inverse operation of a quantum-mechanically reversible multiplier implemented with QA-based Boolean logic circuits. We designed the QA machine on an application-specific-annealing-computing architecture which efficiently increases available hardware budgets at the cost of restricted functionality.…
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We propose a prime factoring machine operated in a frame work of quantum annealing (QA). The idea is inverse operation of a quantum-mechanically reversible multiplier implemented with QA-based Boolean logic circuits. We designed the QA machine on an application-specific-annealing-computing architecture which efficiently increases available hardware budgets at the cost of restricted functionality. The circuits are to be implemented and fabricated by using superconducting integrated circuit technology. We propose a three-dimensional packaging scheme of a qubit-chip / interposer / package-substrate structure for realizing practically-large scale QA systems.
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Submitted 15 December, 2017;
originally announced December 2017.
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Investigation of spin scattering mechanism in silicon channels of Fe/MgO/Si lateral spin valves
Authors:
Soobeom Lee,
Naoto Yamashita,
Yuichiro Ando,
Shinji Miwa,
Yoshishige Suzuki,
Hayato Koike,
Masashi Shiraishi
Abstract:
The temperature evolution of spin relaxation time, τsf, in degenerate silicon (Si)-based lateral spin valves is investigated by means of the Hanle effect measurements. τsf at 300 K is estimated to be 1.68+-0.03 ns and monotonically increased with decreasing temperature down to 100 K. Below 100 K, in contrast, it shows almost a constant value of ca. 5 ns. The temperature dependence of the conductiv…
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The temperature evolution of spin relaxation time, τsf, in degenerate silicon (Si)-based lateral spin valves is investigated by means of the Hanle effect measurements. τsf at 300 K is estimated to be 1.68+-0.03 ns and monotonically increased with decreasing temperature down to 100 K. Below 100 K, in contrast, it shows almost a constant value of ca. 5 ns. The temperature dependence of the conductivity of the Si channel shows a similar behavior to that of the τsf, i.e., monotonically increasing with decreasing temperature down to 100 K and a weak temperature dependence below 100 K. The temperature evolution of conductivity reveals that electron scattering due to magnetic impurities is negligible. A comparison between τsf and momentum scattering time reveals that the dominant spin scattering mechanism in the Si is the Elliott-Yafet mechanism, and the ratio of the momentum scattering time to the τsf attributed to nonmagnetic impurities is approximately 3.77*10^-6, which is more than two orders of magnitude smaller than that of copper.
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Submitted 21 April, 2017;
originally announced April 2017.
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Observation of large spin accumulation voltages in non-degenerate Si spin devices due to spin drift effect: Experiments and theory
Authors:
Takayuki Tahara,
Yuichiro Ando,
Makoto Kameno,
Hayato Koike,
Kazuhito Tanaka,
Shinji Miwa,
Yoshishige Suzuki,
Tomoyuki Sasaki,
Tohru Oikawa,
Masashi Shiraishi
Abstract:
A large spin-accumulation voltage of more than 1.5 mV at 1 mA, i.e., a magnetoresistance of 1.5 Ω, was measured by means of the local three-terminal magnetoresistance in nondegenerate Si-based lateral spin valves (LSVs) at room temperature. This is the largest spin-accumulation voltage measured in semiconductor-based LSVs. The modified spin drift-diffusion model, which successfully accounts for th…
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A large spin-accumulation voltage of more than 1.5 mV at 1 mA, i.e., a magnetoresistance of 1.5 Ω, was measured by means of the local three-terminal magnetoresistance in nondegenerate Si-based lateral spin valves (LSVs) at room temperature. This is the largest spin-accumulation voltage measured in semiconductor-based LSVs. The modified spin drift-diffusion model, which successfully accounts for the spin drift effect, explains the large spin-accumulation voltage and significant bias-current-polarity dependence. The model also shows that the spin drift effect enhances the spin-dependent magnetoresistance in the electric two terminal scheme. This finding provides a useful guiding principle for spin metal-oxide semiconductor field-effect transistor (MOSFET) operations.
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Submitted 5 January, 2016;
originally announced January 2016.
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Room-temperature operation of Si spin MOSFET with high on/off spin signal ratio
Authors:
Takayuki Tahara,
Hayato Koike,
Makoto Kameno,
Yuichiro Ando,
Kazuhito Tanaka,
Shinji Miwa,
Yoshishige Suzuki,
Masashi Shiraishi
Abstract:
We experimentally demonstrate a Si spin metal-oxide-semiconductor field-effect transistor (MOSFET) that exhibits a high on/off ratio of source-drain current and spin signals at room temperature. The spin channel is non-degenerate n-type Si, and an effective application of gate voltage in the back-gated structure allows the spin MOSFET operation. This achievement can pave the way to practical use o…
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We experimentally demonstrate a Si spin metal-oxide-semiconductor field-effect transistor (MOSFET) that exhibits a high on/off ratio of source-drain current and spin signals at room temperature. The spin channel is non-degenerate n-type Si, and an effective application of gate voltage in the back-gated structure allows the spin MOSFET operation. This achievement can pave the way to practical use of the Si spin MOSFET.
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Submitted 22 October, 2015;
originally announced October 2015.
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Spin transport in non-degenerate Si with a spin MOSFET structure at room temperature
Authors:
Tomoyuki Sasaki,
Yuichiro Ando,
Makoto Kameno,
Takayuki Tahara,
Hayato Koike,
Tohru Oikawa,
Toshio Suzuki,
Masashi Shiraishi
Abstract:
Spin transport in non-degenerate semiconductors is expected to pave a way to the creation of spin transistors, spin logic devices and reconfigurable logic circuits, because room temperature (RT) spin transport in Si has already been achieved. However, RT spin transport has been limited to degenerate Si, which makes it difficult to produce spin-based signals because a gate electric field cannot be…
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Spin transport in non-degenerate semiconductors is expected to pave a way to the creation of spin transistors, spin logic devices and reconfigurable logic circuits, because room temperature (RT) spin transport in Si has already been achieved. However, RT spin transport has been limited to degenerate Si, which makes it difficult to produce spin-based signals because a gate electric field cannot be used to manipulate such signals. Here, we report the experimental demonstration of spin transport in non-degenerate Si with a spin metal-oxide-semiconductor field-effect transistor (MOSFET) structure. We successfully observed the modulation of the Hanle-type spin precession signals, which is a characteristic spin dynamics in non-degenerate semiconductor. We obtained long spin transport of more than 20 μm and spin rotation, greater than 4π at RT. We also observed gate-induced modulation of spin transport signals at RT. The modulation of spin diffusion length as a function of a gate voltage was successfully observed, which we attributed to the Elliott-Yafet spin relaxation mechanism. These achievements are expected to make avenues to create of practical Si-based spin MOSFETs.
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Submitted 7 September, 2014;
originally announced September 2014.
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Spin Drift in Highly Doped n-type Si
Authors:
Makoto Kameno,
Yuichiro Ando,
Teruya Shinjo,
Hayato Koike,
Tomoyuki Sasaki,
Tohru Oikawa,
Toshio Suzuki,
Masashi Shiraishi
Abstract:
A quantitative estimation of spin drift velocity in highly doped n-type silicon (Si) at 8 K is presented in this letter. A local two-terminal Hanle measurement enables the detection of a modulation of spin signals from the Si as a function of an external electric field, and this modulation is analyzed by using a spin drift-diffusion equation and an analytical solution of the Hanle-type spin preces…
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A quantitative estimation of spin drift velocity in highly doped n-type silicon (Si) at 8 K is presented in this letter. A local two-terminal Hanle measurement enables the detection of a modulation of spin signals from the Si as a function of an external electric field, and this modulation is analyzed by using a spin drift-diffusion equation and an analytical solution of the Hanle-type spin precession. The analyses reveal that the spin drift velocity is linearly proportional to the electric field. The contribution of the spin drift effect to the spin signals is crosschecked by introducing a modified nonlocal four-terminal method.
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Submitted 15 January, 2014;
originally announced January 2014.
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Local magnetoresistance in Fe/MgO/Si lateral spin valve at room temperature
Authors:
Tomoyuki Sasaki,
Toshio Suzuki,
Yuichiro Ando,
Hayato Koike,
Tohru Oikawa,
Yoshishige Suzuki,
Masashi Shiraishi
Abstract:
Room temperature local magnetoresistance in two-terminal scheme is reported. By employing 1.6 nm-thick MgO tunnel barrier, spin injection efficiency is increased, resulting in large non-local magnetoresistance. The magnitude of the non-local magnetoresistance is estimated to be 0.0057 ohm at room temperature. As a result, a clear rectangle signal is observed in local magnetoresistance measurement…
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Room temperature local magnetoresistance in two-terminal scheme is reported. By employing 1.6 nm-thick MgO tunnel barrier, spin injection efficiency is increased, resulting in large non-local magnetoresistance. The magnitude of the non-local magnetoresistance is estimated to be 0.0057 ohm at room temperature. As a result, a clear rectangle signal is observed in local magnetoresistance measurement even at room temperature. We also investigate the origin of local magnetoresistance by measuring the spin accumulation voltage of each contact separately.
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Submitted 7 January, 2014;
originally announced January 2014.