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  • 14:38 (UTC +08:00)

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@pobu-arch
Pobu pobu-arch
Computer System & Architecture

California

@jiangyy
Yanyan Jiang jiangyy
Associate Professor, Nanjing University

Nanjing University Nanjing, China

@Guo-HY
HongYu Guo Guo-HY
Whatever has been done,can be outdone

ICT,CAS Beijing

@jinyue110
Jenius jinyue110
Ph.D. candidate majoring in Computer Architecture

Institute of Computing Technology ( ICT ) Chinese Academy of Sciences ( CAS ) University of Chinese Academy of Sciences(UCAS), Beijing

@linjuanZ
zhanglinjuan linjuanZ
Computer Architecture M.S. | Lead developer of LSU and cache sub-system of the open-source high-performance RISC-V processor XiangShan

Beijing Institute of Open Source Chip Beijing

@OpenXiangShan
XiangShan OpenXiangShan
Open-source high-performance RISC-V processor
@Lemover
Zifei Zhang Lemover
De-bug or In-bug

UCAS && ICT Beijing

@poemonsense
Yinan Xu poemonsense
Life is short, work hard

Institute of Computing Technology, CAS Beijing

@shinezyy
周耀阳 (Zhou Yaoyang) shinezyy
Deep Learning performance architect; Former CPU perf Arch; PhD in computer architecture; Husband & Father
@chenguokai
Xim chenguokai

EPFL Lausanne

@Lingrui98
Steve Gou Lingrui98
Ph.D student of CS major in ICT

Beijing

@wakafa1
wakafa wakafa1
Fight on!

University of Chinese Academy of Sciences Beijing

@sequencer
Jiuyang Liu sequencer
0x8D7B5A. I work for open source chip design.

Wuhan, China

@huangqundl
HUANG Qun huangqundl

Peking University Beijing, China

@DanDoge
DanDoge DanDoge

Peking University -> ETH Zürich Zürich, Switzerland

@JF-D
JFDuan JF-D
Interested in AI for system, efficient LLM training and serving!

Ph.D. Candidate@CUHK-MMLab, B.E.@ UCAS HongKong

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