Tags: riscv/sail-riscv
Tags
Reduce code nesting in `run_hart_active` for simplicity. (#1570) When triggers need to be handled for Sdtrig, they need to be considered in conjunction with pending interrupts. This minor refactor reduces the code churn to handle that case.
Log Sail exceptions into the execution trace. (#1555) With a thrown Sail exception, the log now terminates with something like: ``` [119] [M]: 0x000000008000200E (0x10A29073) csrrw x0, senvcfg, x5 main+14 Fatal reserved behavior: xenvcfg.CBIE = 0b10 Exiting due to uncaught exception: prelude/errors.sail:28.2-28.41 ``` where previously it would only show ``` [119] [M]: 0x000000008000200E (0x10A29073) csrrw x0, senvcfg, x5 main+14 Exiting due to uncaught exception: prelude/errors.sail:28.2-28.41 ``` This fixes #1553.
Add the Zibi extension. (#1507) Add the Zibi extension, which adds conditional branch instructions to compare with small immediates. This extension isn't ratified yet so it is gated behind the `--enable-experimental-extensions` flag. Spec: https://github.com/riscv/zibi/releases/ More info: riscv/zibi#2
Add configuration option for reserved behavior: odd number register f… …or RV32Zdinx (#1462) Add configuration option for reserved behavior: odd number register for RV32Zdinx. It allows two options: a fatal error that stops the simulation, or to treat it as an illegal instruction (the default choice). similar to that in #1403.
Centralize memory-access-to-fault conversions. (#1475) There were multiple conversions scattered around the model. Some used wild-cards, making it easy to miss correct handling when adding a new memory access type, or causing duplicated effort when changing memory access handling.
PreviousNext