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rv32e

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Ad1thh / Final-Project-EV

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Synthesizable 3-stage pipelined RV32E RISC-V processor core in SystemVerilog-2012 for Artix-7 FPGA (Nexys 4) and ASIC. Features hazard forwarding, 32KB BRAM, MMIO LED peripherals, 100% RISC-V ACT 4.0 compliance (195/195 tests passed), live silicon validation, and ongoing ECC SEC-DED fault-tolerance & Cadence Genus ASIC synthesis extensions.

fpga fault-tolerance systemverilog fault-injection risc-v xilinx-vivado tmr compliance-testing rv32e asic-design nexys4-board cadence-innovus cadence-xcelium cadence-genus sec-ded
  • Updated Aug 23, 2026
  • SystemVerilog

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