#
nexys4
Here are 8 public repositories matching this topic...
This project is to implement a combination lock on the FPGA board using VHDL language and finite state machine. There are some possible solutions are provided to address the problems including debounce, random number generation and combination check.
vhdl finite-state-machine vivado digital-design debounce-button nexys4 random-numbers combination-lock multi-digits-display
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Jul 29, 2020 - VHDL
A FPGA Based Square Root Approximation Coprocessor
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Jul 13, 2020 - VHDL
Designed and Implemented a low pass filter in Nexys 4 FPGA
fpga dsp matlab simulink digital-signal-processing xilinx-fpga filter-design xilinx-vivado nexys4 lowpass-filter
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Jul 30, 2020 - VHDL
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