An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
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Feb 14, 2022 - C
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fpga-accelerator
Here are 60 public repositories matching this topic...
QKeras: a quantization deep learning library for Tensorflow Keras
machine-learning fpga deep-learning tensorflow accelerator keras quantization hardware-acceleration fpga-accelerator quantized-neural-networks asic-design quantized-networks
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Jun 13, 2025 - Python
Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
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Apr 22, 2019 - Jupyter Notebook
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
linux iot fpga zynq tensorflow assembly vhdl embedded-systems internet-of-things hardware-architectures verilog xilinx vivado tensor hardware-designs hardware-acceleration fpga-accelerator hardware-description-language ip-core tpu
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Jan 5, 2019 - VHDL
Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.
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Jun 27, 2018 - Objective-C
Research and Materials on Hardware implementation of Transformer Model
natural-language-processing fpga accelerator transformer gpu-acceleration pretrained-models hardware-designs research-paper bert fpga-accelerator systolic-arrays processing-in-memory vision-transformer video-transformer
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Feb 28, 2025 - Jupyter Notebook
Convolutional accelerator kernel, target ASIC & FPGA
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Apr 10, 2023 - Verilog
Small-scale Tensor Processing Unit built on an FPGA
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Aug 4, 2019 - Verilog
BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
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Jan 5, 2025 - Tcl
This project implements a convolution kernel based on vivado HLS on zcu104
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Mar 15, 2020 - C++
OPAE porting to Xilinx FPGA devices.
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Aug 5, 2020 - Coq
OpenGL 1.x implementation for FPGAs
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Dec 23, 2025 - C++
OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.
fpga opencl altera-opencl-sdk fpga-accelerator darknet-image-classification de10-nano cnn-acceleration neural-network-accelerator intel-fpga-opencl
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Oct 3, 2023 - C
Lenet for MNIST handwritten digit recognition using Vivado hls tool
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Jul 22, 2020 - Objective-C
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
signal-processing fast-fourier-transform digital-signal-processing vlsi-physical-design fpga-accelerator vlsi-design vlsi-project
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May 20, 2020 - Verilog
Co-processor for whole genome alignment
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Jun 6, 2020 - Verilog
An automated HDC platform
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Dec 22, 2025 - VHDL
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
asic fpga ip verilog binary-tree systemverilog binary-trees bst fpga-accelerator bstree asic-design svut
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Sep 5, 2021 - SystemVerilog
Hardware-accelerated sorting algorithm
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May 4, 2020 - VHDL
TCP/IP and UDP/IP protocol stack off-loading
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Aug 9, 2020 - Verilog
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