wishbone-bus

Star

Here are 31 public repositories matching this topic...

ZipCPU / s6soc

Star

8000

CMod-S6 SoC

fpga fpga-soc wishbone verilator zipcpu wishbone-bus

Updated Jan 6, 2018
Verilog

zz-systems / Plasma-SoC

Star

Plasma MIPS (I) SoC

cpu mips de1-soc zedboard wishbone system-on-chip wishbone-bus

Updated Sep 17, 2018
C

pbing / J1_WB

Star

Forth CPU J1 in SystemVerilog and Wishbone interface

systemverilog wishbone wishbone-bus forth-cpu

Updated Oct 3, 2018
SystemVerilog

ZipCPU / xulalx25soc

Star

A System on a Chip Implementation for the XuLA2-LX25 board

fpga soc zipcpu wishbone-bus

Updated Dec 13, 2018
Verilog

semahawk / wishbone

Star

Trying to learn Wishbone by implementing few master/slave devices

verilog verilog-hdl wishbone wishbone-bus

Updated Jan 7, 2019
SystemVerilog

semahawk / icarium

Star

Trying to implement a soft core SoC

verilog verilog-hdl wishbone soft-core system-on-chip softcore wishbone-bus

Updated Apr 6, 2019
Verilog

jakubcabal / rmii-firewall-fpga

Sponsor

Star

RMII Firewall FPGA

fpga firewall vhdl ethernet wishbone-bus rmii cyc1000

Updated Dec 2, 2019
VHDL

cyber-murmel / nmigen-wishbone-examples

Sponsor

Star

A collection of nMigen examples based on the OpenCores WISHBONE Tutorial https://cdn.opencores.org/downloads/wbspec_b4.pdf#page=91

fpga fpga-soc wishbone wishbone-bus nmigen nmigen-soc

Updated Nov 6, 2020
Python

rlee287 / hardware-bus-infrastructure

Star

A collection of formal properties for hardware buses, and cores using them.

psl sva wishbone-bus axi4 axi4-lite axi4-stream bus-standards

Updated Feb 22, 2021
Verilog

jakubcabal / uart-for-fpga

Sponsor

Star

Simple UART controller for FPGA written in VHDL

fpga simulation controller vhdl uart ghdl wishbone uart-controller wishbone-bus cyc1000 uart-loopback

Updated Aug 7, 2021
VHDL

pbing / Wishbone

Star

Check Wishbone B4 variants

systemverilog wishbone wishbone-bus

Updated Feb 4, 2023
SystemVerilog

ZipCPU / wbscope

Star

A wishbone controlled scope for FPGA's

fpga verilog debugging-tools wishbone verilator wishbone-bus

Updated Jan 12, 2024
Verilog

ZipCPU / wbfmtx

Star

A wishbone controlled FM transmitter hack

fpga hack verilog wishbone verilog-components wishbone-bus fm-transmitter

Updated Jan 16, 2024
Verilog

ZipCPU / openarty

Star

An Open Source configuration of the Arty platform

fpga fpga-soc wishbone verilator arty zipcpu wishbone-bus

Updated Jan 17, 2024
Verilog

ZipCPU / dbgbus

Star

A collection of debugging busses developed and presented at zipcpu.com

verilog debugging-tools wishbone fgpa verilator wishbone-bus

Updated Jan 18, 2024
Verilog

ZipCPU / wbuart32

Star

A simple, basic, formally verified UART controller

fpga verilog uart serialport uart-verilog wishbone verilator wishbone-bus

Updated Jan 29, 2024
Verilog

ZipCPU / wbi2c

Star

Wishbone controlled I2C controllers

fpga i2c gplv3 verilog verilator i2c-slave wishbone-bus i2c-master

Updated Nov 12, 2024
Verilog

alinja / alpus_wb

Star

VHDL implementation of Pipelined Wishbone B4 interconnect

fpga bus vhdl soc fpga-soc wishbone system-on-chip interconnect wishbone-bus

Updated Dec 5, 2024
VHDL

ZipCPU / autofpga

Star

A utility for Composing FPGA designs from Peripherals

c-plus-plus fpga verilog wishbone verilator wishbone-bus

Updated Dec 23, 2024
C++

alinja / alpus_spi_slave

Star

VHDL SPI slave, providing Wishbone bus master

fpga vhdl spi wishbone wishbone-bus

Updated Jan 5, 2025
VHDL

Improve this page

Add a description, image, and links to the wishbone-bus topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the wishbone-bus topic, visit your repo's landing page and select "manage topics."

Learn more

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

wishbone-bus

Here are 31 public repositories matching this topic...

ZipCPU / s6soc

zz-systems / Plasma-SoC

pbing / J1_WB

ZipCPU / xulalx25soc

semahawk / wishbone

semahawk / icarium

jakubcabal / rmii-firewall-fpga

cyber-murmel / nmigen-wishbone-examples

rlee287 / hardware-bus-infrastructure

jakubcabal / uart-for-fpga

pbing / Wishbone

ZipCPU / wbscope

ZipCPU / wbfmtx

ZipCPU / openarty

ZipCPU / dbgbus

ZipCPU / wbuart32

ZipCPU / wbi2c

alinja / alpus_wb

ZipCPU / autofpga

alinja / alpus_spi_slave

Improve this page

Add this topic to your repo