RISC-V Ibex core with Wishbone B4 interface
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Apr 27, 2025 - SystemVerilog
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wishbone-bus
Here are 6 public repositories matching this topic...
Trying to learn Wishbone by implementing few master/slave devices
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Jan 7, 2019 - SystemVerilog
Forth CPU J1 in SystemVerilog and Wishbone interface
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Oct 3, 2018 - SystemVerilog
A compact SystemVerilog SoC implementing a RV32IM CPU with memory‑mapped GPIO, UART and Timer peripherals on a Wishbone bus. Instruction memory is JTAG‑programmable and the repo includes Verilator testbenches plus a gcc-based toolchain to build C programs and generate Verilog‑readable instruction images.
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Nov 5, 2025 - SystemVerilog
A simple UART Controller written in SystemVerilog
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Aug 7, 2025 - SystemVerilog
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