Intel Quartus workflow assistant for FPGA/VHDL developers
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Aug 26, 2026 - TypeScript
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questasim
Here are 79 public repositories matching this topic...
VGA IP-core with AXI Video Stream interface.
fpga rtl verilog hdl modelsim questasim axis vga verilog-hdl vga-controller fpga-programming axis-video-stream
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Aug 25, 2026 - Verilog
Dual port BRAM module for FPGA. VHDL and Verilog versions.
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Aug 21, 2026 - VHDL
IP-core for waveform generations with unsigned output.
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Aug 21, 2026 - Verilog
VS Code extension to replace Questasim. User-friendly VHDL-2008 code editor with testbenches simualtion, FSM graphic designer, RTL schematization and precise error detection.
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Aug 19, 2026 - JavaScript
Simulation and implementation flow for hardware description languages
asic fpga simulation vhdl verilog vivado systemverilog implementation questasim quartus systemrdl cocotb synopsys-vcs
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Aug 18, 2026 - Python
Functional verification of a synchronous FIFO — spec-driven testplan, coverage model, and SystemVerilog testbench in QuestaSim.
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Aug 16, 2026 - SystemVerilog
This repository compiles notes, fixes, and configuration files that address common issues and bugs encountered during the installation and use of various software tools on both Linux and Windows platforms.
zynq xilinx altera de1-soc questasim xilinx-fpga xilinx-vivado quartus-prime altera-fpga tang gowin altera-quartus tang-primer gowin-eda monitor-program
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Aug 3, 2026 - HTML
VHDL RTL design exercises covering counters, synchronization, FSM control and APB integration.
github git fpga vhdl finite-state-machine questasim digital-design clock-domain-crossing tcl-scripts seven-segment-display amba-apb asic-design rtl-design vhdl-2008
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Jul 28, 2026 - VHDL
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Jul 22, 2026 - Verilog
SystemVerilog-based UART verification project featuring a layered testbench architecture, constrained-random stimulus generation, transaction-based verification, assertions, and a self-checking scoreboard for protocol validation.
assertions systemverilog questasim uart-protocol digital-design design-verification uart-verification
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Jul 17, 2026 - SystemVerilog
The RTL implementation of a 8-bit pipelined signed integer multiplication module with some optimization techniques and testbench.
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Jul 14, 2026 - SystemVerilog
Synthesizable AHB5-to-APB5 bridge and 4KB APB SRAM with layered UVM 1.2 verification, assertions, coverage closure, and Questa automation.
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Jul 11, 2026 - JavaScript
Repurposing existing HDL tools to help writing better code
python vim language-server vhdl verilog xilinx syntax-checker systemverilog hdl modelsim questasim ghdl xilinx-vivado lsp-server coc-nvim vim-ale vivado-simulator mentor-msim hdl-checker emacs-lsp
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Jun 21, 2026 - Python
A 32-bit RISC-V processor implemented in SystemVerilog featuring a custom 3-stage pipeline architecture, support for major RV32I instruction formats, simulation-based verification, and successful deployment on FPGA hardware.
cpu fpga systemverilog computer-architecture questasim risc-v digital-design rtl-design pipelined-processors
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Jun 21, 2026 - SystemVerilog
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