AluVM: RISC functional machine base implementation
A RISC-V virtual processor, written in Rust.
BELLE (Big Endian, Low Level Emulator) The monorepo for a custom 16 bit RISC architecture.
OpenID Shared Signals (SSF/CAEP/RISC) and Security Event Tokens
A interpreter (VM) for the U-RISC instruction-set
Mips disassembler written in Rust
Stack based interpreter
A simple computer architeture, ISA and Interpreter build with Rust.
RISC-V 32-bit ZK virtual machine with conditional ZK proofs & proofs aggregation via STARKY / PLONKY2
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