Advanced Matrix Extensions (AMX) Guide
UME::SIMD A library for explicit simd vectorization.
Kite: Architecture Simulator for RISC-V Instruction Set
My very own CPU architecture! Emulator availible!
An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer
RISCAL is a 32-bit reduced instruction-set computer (RISC) designed for learning and research purposes. It is named after my dog, Rascal.
Intrinsics are high level functions implemented in C language and are based in some ISAs. The mainly purpose is simulate these architectures in SiNUCA (Simulator of Non-Uniforme Caches)..
C++ basic instruction set simulator
Create and represent instruction sets in code easily.
A simple RV32I RISC-V CPU emulator in C++ supporting: ADDI, ADD, SUB, MUL, MULH, SRAI , LW, SW, LUI, JAL , ECALL (program exit) - ELF loader for test programs ,Instruction trace for debugging
SRP16 is free and open ISA for 16-bit CPUs and Microcontrollers.
Phasor Programming Language and Toolchain (Beta)
Repository for the CENG513 Course that I have taken at IZTECH
A two-pass assembler and emulator implementation in C++ for a custom instruction set architecture. This project demonstrates the complete process of assembly language processing, from source code parsing to machine code execution.
8-bit ISA standard with a Verilog core implementation, assembler and JIT emulator/debugger
C++26 Custom Instruction Set Architecture Framework
We develop a physical computer programming language using Arduino microcontroller board.
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