VeeR EH1 core
VeeR EL2 Core
DUTH RISC-V Superscalar Microprocessor
Minimalistic RV32I RISC-V Processor in System Verilog
DUTH RISC-V Microprocessor
Arquivos base para o projeto das disciplinas IF674 e CIN0012 no CIn-UFPE.
Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.
A 5-Stage Pipelined RISC-V Processor designed and implemented on FPGA (Artix-7 Nexys A7). Supports RV32I instructions set (R, I, S, B, U, J types) with ALU, control unit, hazard detection, forwarding, and pipeline registers. Verified through simulation and hardware testing with optimized timing and 4× performance gain.
A RISC-V RV32IM CPU and SoC built from scratch in SystemVerilog — single-cycle → 5-stage pipeline, caches, AXI4 + DDR, HDMI — running DOOM on a Zybo Z7-20. Spike-verified, Verilator-simulated.
A fully pipelined 5-stage RV32I processor implemented in SystemVerilog. This design models instruction-level parallelism with forwarding and hazard detection, and passes all RISCOF compliance tests for the RV32I base ISA.
Методичка по высшей цифровой схемотехнике + Verilog
Simple RISC-V Pipelined processor implemented on SystemVerilog.
RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.
CompactRISC (CR16) CPU (with an assembler) for the Computer Design Laboratory ECE 3710 class at The University of Utah
Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.
A Developer version MIPS processor.
4 stage pipeline implementation of a 16-bit RISC Processor in SystemVerilog that performs arithmetical, logical, data transfer, branch and halt operations.
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