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Physics > Applied Physics

arXiv:2005.05237 (physics)
[Submitted on 11 May 2020]

Title:Charge trap layer enabled positive tunable V$_{fb}$ in $β$-Ga$_{2}$O$_{3}$ gate stacks for enhancement mode transistors

Authors:Dipankar Biswas, Chandan Joishi, Jayeeta Biswas, Prabhans Tiwari, Saurabh Lodha
View a PDF of the paper titled Charge trap layer enabled positive tunable V$_{fb}$ in $\beta$-Ga$_{2}$O$_{3}$ gate stacks for enhancement mode transistors, by Dipankar Biswas and 3 other authors
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Abstract:$\beta$-Ga$_{2}$O$_{3}$ based enhancement mode transistor designs are critical for the realization of low loss, high efficiency next generation power devices with rudimentary driving circuits. A novel approach towards attaining a high positive flat band voltage (V$_{fb}$) of 10.6 V in $\beta$-Ga$_{2}$O$_{3}$ metal-oxide-semiconductor capacitors (MOSCAPs), with the ability to fine tune it between 3.5 V to 10.6 V, using a polycrystalline AlN charge trap layer has been demonstrated. This can enable enhancement mode operation over a wide doping range. Excellent V$_{fb}$ retention of ${\sim}$97% for 10$^{4}$ s at 55 $^{\circ}$C was exhibited by the gate stacks after charge trapping, hence reducing the requirement of frequent charge injection cycles. In addition, low gate leakage current density (J$_{g}$) for high negative gate voltages (V$_{g}$${\sim}$-60 V) indicates the potential of this gate stack to enable superior breakdown characteristics in enhancement mode transistors.
Comments: Single file (Manuscript and Supplementary material combined) of 19 pages. Total 5 and 4 figures in manuscript and supplementary material, respectively
Subjects: Applied Physics (physics.app-ph); Materials Science (cond-mat.mtrl-sci)
Cite as: arXiv:2005.05237 [physics.app-ph]
  (or arXiv:2005.05237v1 [physics.app-ph] for this version)
  https://doi.org/10.48550/arXiv.2005.05237
arXiv-issued DOI via DataCite
Related DOI: https://doi.org/10.1063/5.0014813
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From: Saurabh Lodha [view email]
[v1] Mon, 11 May 2020 16:29:44 UTC (1,866 KB)
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