Showing 1–2 of 2 results for author: Halsey, C

Direct integration of atomic precision advanced manufacturing into middle-of-line silicon fabrication

Authors: E. M. Anderson, C. R. Allemang, A. J. Leenheer, S. W. Schmucker, J. A. Ivie, D. M. Campbell, W. Lepkowski, X. Gao, P. Lu, C. Arose, T. -M. Lu, C. Halsey, T. D. England, D. R. Ward, D. A. Scrymgeour, S. Misra

Abstract: Atomic precision advanced manufacturing (APAM) dopes silicon with enough carriers to change its electronic structure and can be used to create novel devices by defining metallic regions whose boundaries have single-atom abruptness. Incompatibility with the thermal and lithography process requirements for gated silicon transistor manufacturing have inhibited exploration of both how APAM can enhance… ▽ More Atomic precision advanced manufacturing (APAM) dopes silicon with enough carriers to change its electronic structure and can be used to create novel devices by defining metallic regions whose boundaries have single-atom abruptness. Incompatibility with the thermal and lithography process requirements for gated silicon transistor manufacturing have inhibited exploration of both how APAM can enhance CMOS performance and how transistor manufacturing steps can accelerate the discovery of new APAM device concepts. In this work, we introduce an APAM process that enables direct integration into the middle of a transistor manufacturing workflow. We show that a process that combines sputtering and annealing with a hardmask preserves a defining characteristic of APAM, a doping density far in excess of the solid solubility limit, while trading another, the atomic precision, for compatibility with manufacturing. The electrical characteristics of a chip combining a transistor with an APAM resistor show that the APAM module has only affected the transistor through the addition of a resistance and not by altering the transistor. This proof-of-concept demonstration also outlines the requirements and limitations of a unified APAM tool, which could be introduced into manufacturing environments, greatly expanding access to this technology and inspiring a new generation of devices with it. △ Less

Submitted 15 October, 2025; v1 submitted 6 May, 2025; originally announced May 2025.

Comments: This article has been published by Applied Physics Reviews at https://pubs.aip.org/aip/apr/article/12/4/041402/3366930/Direct-integration-of-atomic-precision-advanced as part of Special Collection: Advances on Manufacturing and Next-generation Devices Towards CHIPS Act https://pubs.aip.org/apr/collection/433328/Advances-on-Manufacturing-and-Next-generation. Copyright 2025 Authors

Report number: SAND2025-05438O, SAND2025-13135J

Journal ref: Applied Physics Reviews, 12, 041402 (2025)

Accelerated Lifetime Testing and Analysis of Delta-doped Silicon Test Structures

Authors: Connor Halsey, Jessica Depoy, DeAnna M. Campbell, Daniel R. Ward, Evan M. Anderson, Scott W. Schmucker, Jeffrey A. Ivie, Xujiao Gao, David A. Scrymgeour, Shashank Misra

Abstract: As transistor features shrink beyond the 2 nm node, studying and designing for atomic scale effects become essential. Being able to combine conventional CMOS with new atomic scale fabrication routes capable of creating 2D patterns of highly doped phosphorus layers with atomic precision has implications for the future of digital electronics. This work establishes the accelerated lifetime tests of s… ▽ More As transistor features shrink beyond the 2 nm node, studying and designing for atomic scale effects become essential. Being able to combine conventional CMOS with new atomic scale fabrication routes capable of creating 2D patterns of highly doped phosphorus layers with atomic precision has implications for the future of digital electronics. This work establishes the accelerated lifetime tests of such doped layers, showing that these materials survive high current (>3.0 MA/cm2) and 300$^{\circ}$C for greater than 70 days and are still electrically conductive. The doped layers compare well to failures in traditional metal layers like aluminum and copper where mean time to failure at these temperatures and current densities would occur within hours. It also establishes that these materials are more stable than metal features, paving the way toward their integration with operational CMOS. △ Less

Submitted 24 February, 2022; v1 submitted 22 October, 2021; originally announced October 2021.

Comments: In IEEE Trans. Dev. Mater. Rel. (2022). Copyright 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, including reprinting/republishing this material for advertising or promotional purposes, collecting new collected works for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works