BibTeX records: Yoonjee Nam

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@inproceedings{DBLP:conf/vlsic/ChaeCLCYNHLLSSL19,
  author       = {Kwanyeob Chae and
                  JongRyun Choi and
                  Hyungkwon Lee and
                  Jinho Choi and
                  Shinyoung Yi and
                  Yoonjee Nam and
                  Sangyun Hwang and
                  Joohyung Lee and
                  Won Lee and
                  Kihwan Seong and
                  Joohee Shin and
                  Soo{-}Min Lee and
                  Seokkyun Ko and
                  Jihun Oh and
                  Billy Koo and
                  Sanghune Park and
                  Jongshin Shin and
                  Hyungjong Ko},
  title        = {An 8nm All-Digital 7.3Gb/s/pin {LPDDR5} {PHY} with an Approximate
                  Delay Compensation Scheme},
  booktitle    = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
  pages        = {96},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.23919/VLSIC.2019.8777959},
  doi          = {10.23919/VLSIC.2019.8777959},
  timestamp    = {Wed, 06 May 2026 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/ChaeCLCYNHLLSSL19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/LeeOCKKKCNPLKJC17,
  author       = {Soo{-}Min Lee and
                  Jihun Oh and
                  Jinho Choi and
                  Seokkyun Ko and
                  Daero Kim and
                  Kyounghoi Koo and
                  JongRyun Choi and
                  Yoonjee Nam and
                  Sangsoo Park and
                  Hyungkweon Lee and
                  Eunsu Kim and
                  Sukhyun Jung and
                  Kwanyeob Chae and
                  SuHo Kim and
                  Sanghune Park and
                  Sanghyun Lee and
                  Sungho Park},
  title        = {23.6 {A} 0.6V 4.266Gb/s/pin {LPDDR4X} interface with auto-DQS cleaning
                  and write-VWM training for memory controller},
  booktitle    = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2017, San Francisco, CA, USA, February 5-9, 2017},
  pages        = {398--399},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ISSCC.2017.7870429},
  doi          = {10.1109/ISSCC.2017.7870429},
  timestamp    = {Thu, 02 Apr 2026 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LeeOCKKKCNPLKJC17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/esscirc/ChaeCYLJKYNCPL16,
  author       = {Kwanyeob Chae and
                  JongRyun Choi and
                  Shinyoung Yi and
                  Won Lee and
                  Sanghoon Joo and
                  Hyunhyuck Kim and
                  Hyungkwon Yi and
                  Yoonjee Nam and
                  Jinho Choi and
                  Sanghune Park and
                  Sanghyun Lee},
  title        = {A 690mV 4.4Gbps/pin all-digital {LPDDR4} {PHY} in 10nm FinFET technology},
  booktitle    = {{ESSCIRC} Conference 2016: 42\({}^{\mbox{nd}}\) European Solid-State
                  Circuits Conference, Lausanne, Switzerland, September 12-15, 2016},
  pages        = {461--464},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ESSCIRC.2016.7598341},
  doi          = {10.1109/ESSCIRC.2016.7598341},
  timestamp    = {Thu, 16 Jan 2025 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/esscirc/ChaeCYLJKYNCPL16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}