Ansys Path FX

Ansys VeloceRF shortens the design cycle by greatly reducing the time it takes to synthesize and model complex spiral devices and T-lines. It takes only a few seconds to compile an inductor or transformer geometry, and just a couple of minutes to model and analyze it. It integrates with leading EDA platforms, instantiating ready-to-tape-out layouts. Ansys VeloceRF allows you to synthesize devices with tight packing of multiple devices and lines for an optimized silicon floorplan. Analysis of the coupling among any number of inductive devices before detailed layout will reduce design size and reduce or eliminate guard rings. Inductor size as well as inductor-to-inductor crosstalk can impact the die size. Ansys VeloceRF helps you design smaller devices through the use of optimization criteria and geometry constraints. In addition, it calculates coupling among any number of inductors to better optimize silicon real estate and to optimize inductors in circuit context.

Ansys PathFinder-SC is a high-capacity solution to help you plan, verify and sign-off IP and full-chip SoC designs for integrity and robustness against electrostatic discharge (ESD). Ansys PathFinder-SC identifies and isolates the root causes of design issues that can cause chip failure from charged-device model (CDM), human body model (HBM), or other ESD events. It’s high-capacity, cloud-native architecture can enlist thousands of compute cores for fast full-chip turnaround. PathFinder-SC is certified by major foundries for current density checks and ESD sign-off. PathFinder-SC’s integrated data modeling, extraction and transient simulation engine is an end-to end solution for ESD verification. The single-pass use model reads industry-standard design formats, sets up ESD rules, extracts the RCs for the power network, and performs ESD simulations to analyze root causes and provide fix and optimization feedback, all within a single tool.