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Hongce Zhang
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2020 – today
- 2026
- [c31]Mingkai Miao, Jianheng Tang, Guangyu Hu, Hongce Zhang
:
BDD2Seq: Enabling Scalable Reversible-Circuit Synthesis via Graph-to-Sequence Learning. AAAI 2026: 863-872 - [c30]Xiaofeng Zhou
A - tt IC3: Learning-Guided Adaptive Inductive Generalization for Hardware Model Checking. CAV (1) 2026: 357-379 - [c29]Rongliang Fu, Wei Xuan
eLogic: An E-Graph-based Logic Rewriting Framework for Majority-Inverter Graphs. DATE 2026: 1-6 - [c28]Ziyi Yang, Guangyu Hu, Xiaofeng Zhou, Mingkai Miao, Changyuan Yu, Wei Zhang, Hongce Zhang
FORWORD: Accelerating Formal Datapath Verification via Word-Level Sweeping. DATE 2026: 1-7 - [c27]Xiaofeng Zhou, Linfeng Du, Guangyu Hu, Sharad Sinha, Hongce Zhang
AutoINV: Automated Invariant Generation Framework for Formal Verification on High-Level Synthesis Designs. FCCM 2026: 257 - [c26]Chen Chen
ReVEAL: GNN-Guided Reverse Engineering for Formal Verification of Optimized Multipliers. TACAS (2) 2026: 309-333 - [c25]Guangyu Hu
EvolveGen : Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning. TACAS (2) 2026: 334-352 - [d1]Xiaofeng Zhou
Artifact for "A-IC3: Learning-Guided Adaptive Inductive Generalization for Hardware Model Checking" (CAV 2026). Zenodo, 2026 - [i22]Guangyu Hu, Xiaofeng Zhou, Wei Zhang, Hongce Zhang
EvolveGen: Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning. CoRR abs/2602.22609 (2026) - [i21]Mingkai Miao, Guangyu Hu, Wei Zhang, Hongce Zhang
LeGend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking. CoRR abs/2602.24010 (2026) - [i20]Guangyu Hu, Chen Chen, Xiaofeng Zhou, Jiaxi Zhang, Wei Zhang, Hongce Zhang
AutoPDR: Circuit-Aware Solver Configuration Prediction for Hardware Model Checking. CoRR abs/2603.25048 (2026) - [i19]Mingkai Miao, Guangyu Hu, Ziyi Yang, Hongce Zhang
IC3-Evolve: Proof-/Witness-Gated Offline LLM-Driven Heuristic Evolution for IC3 Hardware Model Checking. CoRR abs/2604.03232 (2026) - [i18]Xiaofeng Zhou, Guangyu Hu, Hongce Zhang
A-IC3: Learning-Guided Adaptive Inductive Generalization for Hardware Model Checking. CoRR abs/2604.21688 (2026) - [i17]Xiaofeng Zhou, Linfeng Du, Guangyu Hu, Sharad Sinha, Hongce Zhang
AutoINV: Automated Invariant Generation Framework for Formal Verification on High-Level Synthesis Designs. CoRR abs/2604.22285 (2026) - [i16]Jingren Wang, Guangyu Hu, Shiju Lin, Hongce Zhang
Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation. CoRR abs/2605.08743 (2026) - [i15]Ziyi Yang, Wenji Fang, Chen Chen, Zhiyao Xie, Hongce Zhang:
CircuitProver: Agentic Lean 4 Theorem Proving with Reusable Circuit Proof Library for Hardware Verification. CoRR abs/2607.27259 (2026) - 2025
- [j4]Wenji Fang
Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(1): 200-213 (2025) - [j3]Shang Liu
RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(4): 1448-1461 (2025) - [c24]Wenji Fang
A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks. ASP-DAC 2025: 505-512 - [c23]Zhiyuan Yan
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. ASP-DAC 2025: 614-621 - [c22]Chen Chen, Guangyu Hu, Cunxi Yu, Yuzhe Ma, Hongce Zhang
E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis. DAC 2025: 1-7 - [c21]Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. DAC 2025: 1-7 - [c20]Zhiyuan Yan, Hongce Zhang
Word-Level Counterexample Reduction Methods for Hardware Verification. DATE 2025: 1-7 - [c19]Ziyue Zheng, Zhiyuan Yan, Xiangchen Meng, Guangyu Hu, Hongce Zhang
Hot-FV: A Semi-Formal Test Generation Framework for RTL Functional Coverage Using Warm Starting States. ICCD 2025: 298-305 - [i14]Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. CoRR abs/2504.09260 (2025) - [i13]Chen Chen, Guangyu Hu, Cunxi Yu, Yuzhe Ma, Hongce Zhang
E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis. CoRR abs/2504.11574 (2025) - [i12]Ziyi Yang, Guangyu Hu, Mingkai Miao, Changyuan Yu, Hongce Zhang
SMT-Sweep: Word-Level Representation Unification for Hardware Verification. CoRR abs/2507.02008 (2025) - [i11]Mingkai Miao, Jianheng Tang, Guangyu Hu, Hongce Zhang
BDD2Seq: Enabling Scalable Reversible-Circuit Synthesis via Graph-to-Sequence Learning. CoRR abs/2511.08315 (2025) - [i10]Changyuan Yu, Wenbin Che, Hongce Zhang
Functional Reduction to Speed Up Bounded Model Checking. CoRR abs/2512.06643 (2025) - [i9]Chen Chen, Daniela Kaufmann, Chenhui Deng, Zhan Song, Hongce Zhang
ReVEAL: GNN-Guided Reverse Engineering for Formal Verification of Optimized Multipliers. CoRR abs/2512.22260 (2025) - 2024
- [c18]Guangyu Hu
DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction. ASPDAC 2024: 262-268 - [c17]Wenji Fang
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. DAC 2024: 62:1-62:6 - [c16]Chen Chen
E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis. DAC 2024: 124:1-124:6 - [c15]Zhiyuan Yan, Min Li, Zhengyuan Shi, Wenjie Zhang, Yingcong Chen, Hongce Zhang:
AsymSAT: Accelerating SAT Solving with Asymmetric Graph-Based Model Prediction. DATE 2024: 1-2 - [c14]Zhiyuan Yan
Word-Level Augmentation of Formal Proof by Learning from Simulation Traces. ICCAD 2024: 115:1-115:9 - [i8]Wenji Fang, Mengming Li, Min Li, Zhiyuan Yan, Shang Liu, Hongce Zhang
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs. CoRR abs/2402.00386 (2024) - [i7]Chen Chen, Guangyu Hu
E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis. CoRR abs/2403.14242 (2024) - [i6]Wenji Fang, Shang Liu, Hongce Zhang
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. CoRR abs/2403.18453 (2024) - [i5]Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. CoRR abs/2411.14436 (2024) - 2023
- [j2]Wenji Fang
r-map: Relating Implementation and Specification in Hardware Refinement Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 5113-5126 (2023) - [c13]Bo-Yuan Huang, Hongce Zhang
INVITED: Generalizing the ISA to the ILA: A Software/Hardware Interface for Accelerator-rich Platforms. DAC 2023: 1-4 - [c12]Wenji Fang
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. ICCAD 2023: 1-9 - [c11]Guangyu Hu
NeuroPDR: Integrating Neural Networks in the PDR Algorithm for Hardware Model Checking. MLCAD 2023: 1-6 - [c10]Wenji Fang
WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification. TACAS (2) 2023: 11-18 - [i4]Zhiyuan Yan, Min Li, Zhengyuan Shi, Wenjie Zhang, Yingcong Chen, Hongce Zhang:
Addressing Variable Dependency in GNN-based SAT Solving. CoRR abs/2304.08738 (2023) - [i3]Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. CoRR abs/2311.08441 (2023) - [i2]Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution. CoRR abs/2312.08617 (2023) - 2021
- [c9]Makai Mann
Pono: A Flexible and Extensible SMT-Based Model Checker. CAV (2) 2021: 461-474 - [c8]Yu Zeng, Bo-Yuan Huang
Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables. ICCAD 2021: 1-9 - [c7]Hongce Zhang
Syntax-Guided Synthesis for Lemma Generation in Hardware Model Checking. VMCAI 2021: 325-349 - 2020
- [c6]Hongce Zhang
Verification of Recurrent Neural Networks for Cognitive Tasks via Reachability Analysis. ECAI 2020: 1690-1697 - [c5]Nina Narodytska, Hongce Zhang
In Search for a SAT-friendly Binarized Neural Network Architecture. ICLR 2020 - [c4]Hongce Zhang
Synthesizing Environment Invariants for Modular Hardware Verification. VMCAI 2020: 202-225
2010 – 2019
- 2019
- [j1]Bo-Yuan Huang
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification. ACM Trans. Design Autom. Electr. Syst. 24(1): 10:1-10:24 (2019) - [c3]Bo-Yuan Huang, Hongce Zhang
ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions. TACAS (1) 2019: 351-357 - 2018
- [c2]Hongce Zhang
ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification. FMCAD 2018: 1-10 - [i1]Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, Sharad Malik:
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification. CoRR abs/1801.01114 (2018) - 2016
- [c1]Jangseop Shin, Hongce Zhang
A hardware-based technique for efficient implicit information flow tracking. ICCAD 2016: 94
Coauthor Index
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last updated on 2026-08-24 23:54 CEST by the dblp team
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