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Phase 4 — sharded sparse matrices across chips #16

@scttfrdmn

Description

@scttfrdmn

Roadmap phase tracker

This issue tracks trnsparse's work on Phase 4 of the trnsci roadmap.

See the suite-level roadmap
for the full phase matrix and cross-project dependencies. A reader-friendly
version lives at trnsci.dev/roadmap/.

What this phase means for trnsparse:
Sparse matrices from large-basis chemistry or PDE discretizations
can have >1B nonzeros. Phase 4 shards the CSR / COO storage
across chips and runs SpMV / SpMM in parallel.

Done means:

  • Row-sharded CSR format; SpMV and SpMM run with cross-chip all-reduce where y depends on rows from multiple shards.
  • Validated on canonical large-sparse test matrices (SuiteSparse).
  • Benchmarks at trnsci.dev/trnsparse/benchmarks/.

Coordination

  • Label: phase-4-multichip — matches the same label in every sub-project.
  • Cross-project dependencies, if any, are called out in the "Done means"
    list above. Link any PRs / child issues here for tracking.

Close this issue when all "Done means" items are satisfied.

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