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"A Multi-Bit PUF Architecture Using a 2T Sub-Threshold Voltage Divider."

Massimo Vatalaro et al. (2025)

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DOI: 10.1109/ISCAS56072.2025.11044271

access: closed

type: Conference or Workshop Paper

metadata version: 2025-10-14

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  - https://dblp.org/rec/conf/iscas/VatalaroRMLC25
Massimo Vatalaro, Raffaele De Rose, Vincenzo Maccaronio, Marco Lanuzza, Felice Crupi:
A Multi-Bit PUF Architecture Using a 2T Sub-Threshold Voltage Divider. ISCAS 2025: 1-5

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last updated on 2025-10-14 19:37 CEST by the dblp team

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