A 14-bit 3 GS/s pipelined ADC featuring an input buffer with replica-based nonlinearity compensation in 28-nm CMOS technology.

Hanrui Zhang 0007 Xi'an Jiaotong University, Department of Microelectronics, China https://orcid.org/0000-0003-1875-0654 Hanrui Zhang Hanrui Zhang 0001 Chinese University of Hong Kong, Hong Kong Google, Inc. Carnegie Mellon University, Pittsburgh, PA, USA Duke University, Durham, NC, USA Tsinghua University, IIIS, Beijing, China https://hanruizha.github.io/ https://orcid.org/0000-0001-8991-0622 Hanrui Zhang 0002 Nanjing University of Science and Technology, School of Computer Science and Engineering, China https://ieeexplore.ieee.org/author/37087014956 https://orcid.org/0000-0001-7107-8161 Hanrui Zhang 0003 Tianjin University, School of Electrical and Information Engineering, China https://ieeexplore.ieee.org/author/37088431835 https://orcid.org/0000-0003-0102-0022 Hanrui Zhang 0004 Columbia University Medical Center, Department of Medicine, Division of Cardiology, New York City, NY, USA https://orcid.org/0000-0001-8655-938X https://www.wikidata.org/entity/Q38329464 Hanrui Zhang 0005 Hohai University, Business School, Changzhou, China Hanrui Zhang 0006 University of Michigan, Department of Computational Medicine and Bioinformatics, Ann Arbor, MI, USA https://orcid.org/0000-0001-9924-0319 https://www.wikidata.org/entity/Q95995773 Hanrui Zhang 0008 Naval University of Engineering, Wuhan, China Hanrui Zhang 0009 Tianjin ChengJian University, School of Control and Mechanical, China Hanrui Zhang 0010 Nanchang University, School of Information and Communication Engineering, China https://orcid.org/0009-0001-1957-0922

Nannan Li Lei Pei Bin Liu 0068 Hanrui Zhang 0007 Jinfu Wang Jie Zhang 0039 Xiaofei Wang Hong Zhang 0009 A 14-bit 3 GS/s pipelined ADC featuring an input buffer with replica-based nonlinearity compensation in 28-nm CMOS technology. 107015 2026 168 Microelectron. J. https://doi.org/10.1016/j.mejo.2025.107015 db/journals/mj/mj168.html#LiPLZWZWZ26 streams/journals/mj

Nannan Li Hanrui Zhang 0007 Bin Liu 0068 Lei Pei Jinfu Wang Huanhuan Qi Jie Zhang 0039 Xiaofei Wang Hong Zhang 0009 A 10-Bit 500-MS/s Pipelined SAR ADC With Nonlinearity-Compensated Open-Loop Amplifier and Parallel Conversion Through Comparator Reusing. 354-358 2025 February 72 IEEE Trans. Circuits Syst. II Express Briefs 2 https://doi.org/10.1109/TCSII.2024.3462557 db/journals/tcasII/tcasII72.html#LiZLPWQZWZ25 streams/journals/tcasII

Hanrui Zhang 0007 Nannan Li Jinfu Wang Zihao Jiao Jie Zhang 0039 Xiaofei Wang Hong Zhang 0009 A 1.25-MHz-BW, 83-dB SNDR Pipelined Noise-Shaping SAR ADC With MASH 2-2 Structure and kT/C Noise Cancellation. 3872-3876 2023 October 70 IEEE Trans. Circuits Syst. II Express Briefs 10 https://doi.org/10.1109/TCSII.2023.3289860 db/journals/tcasII/tcasII70.html#ZhangLWJZWZ23

Hanrui Zhang 0007 Xiaofei Wang Nannan Li Zihao Jiao Liang Chen Di Mu Jie Zhang 0039 Hong Zhang 0009 A 2.5-MHz BW, 75-dB SNDR Noise-Shaping SAR ADC With a 1st-Order Hybrid EF-CIFF Structure Assisted by Unity-Gain Buffer. 1928-1932 2022 30 IEEE Trans. Very Large Scale Integr. Syst. 12 https://doi.org/10.1109/TVLSI.2022.3213365 db/journals/tvlsi/tvlsi30.html#ZhangWLJCMZZ22

Hanrui Zhang 0007 Nannan Li Zihao Jiao Jie Zhang 0039 Xiaofei Wang Hong Zhang 0009 A 1<sup>st</sup>-Order Passive Noise-Shaping SAR ADC with Improved NTF Assisted by Comparator Gain Calibration. 1-5 2021 ISCAS https://doi.org/10.1109/ISCAS51556.2021.9401115 conf/iscas/2021 db/conf/iscas/iscas2021.html#ZhangLJZWZ21 Liang Chen Zihao Jiao Nannan Li Bin Liu 0068 Di Mu Lei Pei Huanhuan Qi Jinfu Wang Xiaofei Wang Hong Zhang 0009 Jie Zhang 0039