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Ashwin Sanjay Lele

◀ ▶ joint publications with Ping-Chun Wu

> Home > Persons > Ashwin Sanjay Lele

Publications

2026
[j8]
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  - journals/jssc/TienWKLSCHCHBKLWLLHTC26
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  - https://dblp.org/rec/journals/jssc/TienWKLSCHCHBKLWLLHTC26
Jen-Chun Tien, Ping-Chun Wu, Win-San Khwa, Ashwin Sanjay Lele, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device. IEEE J. Solid State Circuits 61(1): 211-224 (2026)
2025
[c17]
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  - conf/isscc/KhwaWSCHCHBKLLW25
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Win-San Khwa, Ping-Chun Wu, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Ashwin Sanjay Lele, Jui-Jen Wu, Jen-Chun Tien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
14.2 A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge-AI Devices. ISSCC 2025: 1-3
2024
[j3]
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  - journals/tcasai/JhangKWLWKCHHHCCWC24
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Chuan-Jia Jhang, Win-San Khwa, Ping-Chun Wu, Ashwin Sanjay Lele, Ping-Sheng Wu, Chao-En Ke, Ting-Chien Chiu, Yu-Cheng Hung, Wei-Ting Hsu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Jui-Jen Wu, Meng-Fan Chang:
A 22 nm 10.03-237.99 TOPS/W Time-Digital-Hybrid SRAM Compute-in-Memory AI Accelerator for GNN Edge Device Applications. IEEE Trans. Circuits Syst. Artif. Intell. 1(1): 15-25 (2024)

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last updated on 2026-08-18 00:19 CEST by the dblp team

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