BibTeX records: E. Baylac

• > Home > Persons > E. Baylac

@inproceedings{DBLP:conf/essderc/BerthelonAPBPJD16,
  author       = {R. Berthelon and
                  Fran{\c{c}}ois Andrieu and
                  P. Perreau and
                  E. Baylac and
                  A. Pofelski and
                  Emmanuel Josse and
                  Didier Dutartre and
                  A. Claverie and
                  Michel Haond},
  title        = {Performance and layout effects of SiGe channel in 14nm {UTBB} {FDSOI:}
                  SiGe-first vs. SiGe-last integration},
  booktitle    = {46th European Solid-State Device Research Conference, {ESSDERC} 2016,
                  Lausanne, Switzerland, September 12-15, 2016},
  pages        = {127--130},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ESSDERC.2016.7599604},
  doi          = {10.1109/ESSDERC.2016.7599604},
  timestamp    = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl       = {https://dblp.org/rec/conf/essderc/BerthelonAPBPJD16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/essderc/AndrieuCBPNRBPPSGMBGGCBRPSRJWAVFH14,
  author       = {Fran{\c{c}}ois Andrieu and
                  Mika{\"{e}}l Cass{\'{e}} and
                  E. Baylac and
                  P. Perreau and
                  O. Nier and
                  Denis Rideau and
                  R. Berthelon and
                  Franck Pourchon and
                  A. Pofelski and
                  Barbara De Salvo and
                  C. Gallon and
                  Vincent Mazzocchi and
                  D. Barge and
                  C. Gaumer and
                  O. Gourhant and
                  A. Cros and
                  Vincent Barral and
                  Rossella Ranica and
                  Nicolas Planes and
                  Walter Schwarzenbach and
                  E. Richard and
                  Emmanuel Josse and
                  Olivier Weber and
                  Franck Arnaud and
                  Maud Vinet and
                  Olivier Faynot and
                  Michel Haond},
  title        = {Strain and layout management in dual channel (sSOI substrate, SiGe
                  channel) planar {FDSOI} MOSFETs},
  booktitle    = {44th European Solid State Device Research Conference, {ESSDERC} 2014,
                  Venice Lido, Italy, September 22-26, 2014},
  pages        = {106--109},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ESSDERC.2014.6948769},
  doi          = {10.1109/ESSDERC.2014.6948769},
  timestamp    = {Tue, 29 Oct 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/essderc/AndrieuCBPNRBPPSGMBGGCBRPSRJWAVFH14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}