<?xml version="1.0" encoding="UTF-8"?>
<result>
<query id="681775">test*</query>
<status code="200">OK</status>
<time unit="msecs">14.23</time>
<completions total="534" computed="100" sent="10">
<c sc="53846" dc="50438" oc="53846" id="72024911">test</c>
<c sc="45929" dc="45048" oc="45929" id="72025219">testing</c>
<c sc="8485" dc="8381" oc="8485" id="72025367">tests</c>
<c sc="4569" dc="4544" oc="4569" id="72025010">testbed</c>
<c sc="1480" dc="1466" oc="1480" id="72024929">testability</c>
<c sc="924" dc="916" oc="924" id="72024937">testable</c>
<c sc="626" dc="624" oc="626" id="72025015">testbeds</c>
<c sc="521" dc="509" oc="521" id="72024922">testa</c>
<c sc="512" dc="506" oc="512" id="72025103">tester</c>
<c sc="362" dc="360" oc="362" id="72025079">teste</c>
</completions>
<hits total="110758" computed="400" sent="100" first="300">
<hit score="3" id="6173595">
<info><authors><author pid="87/5498">Yoshinobu Higami</author><author pid="44/2540">Hiroshi Furutani</author><author pid="04/10696">Takao Sakai</author><author pid="98/4639">Shuichi Kameyama</author><author pid="54/2994">Hiroshi Takahashi</author></authors><title>Test Pattern Selection for Defect-Aware Test.</title><venue>Asian Test Symposium</venue><pages>102-107</pages><year>2011</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/ats/HigamiFSKT11</key><doi>10.1109/ATS.2011.24</doi><ee>https://doi.org/10.1109/ATS.2011.24</ee><url>https://dblp.org/rec/conf/ats/HigamiFSKT11</url></info>
<url>URL#6173595</url>
</hit>
<hit score="3" id="6173614">
<info><authors><author pid="27/1167">Elham K. Moghaddam</author><author pid="53/6555">Janusz Rajski</author><author pid="r/SudhakarMReddy">Sudhakar M. Reddy</author><author pid="66/10695">Jakub Janicki</author></authors><title>Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating.</title><venue>Asian Test Symposium</venue><pages>267-272</pages><year>2011</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/ats/MoghaddamRRJ11</key><doi>10.1109/ATS.2011.46</doi><ee>https://doi.org/10.1109/ATS.2011.46</ee><url>https://dblp.org/rec/conf/ats/MoghaddamRRJ11</url></info>
<url>URL#6173614</url>
</hit>
<hit score="3" id="6173621">
<info><authors><author pid="20/8338">Brandon Noia</author><author pid="c/KrishnenduChakrabarty">Krishnendu Chakrabarty</author></authors><title>Testing and Design-for-Testability Techniques for 3D Integrated Circuits.</title><venue>Asian Test Symposium</venue><pages>474-479</pages><year>2011</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/ats/NoiaC11a</key><doi>10.1109/ATS.2011.67</doi><ee>https://doi.org/10.1109/ATS.2011.67</ee><url>https://dblp.org/rec/conf/ats/NoiaC11a</url></info>
<url>URL#6173621</url>
</hit>
<hit score="3" id="6173626">
<info><authors><author pid="03/10696">Mohammed Abdul Razzaq</author><author pid="31/4795">Virendra Singh</author><author pid="s/AditDSingh">Adit D. Singh</author></authors><title>SSTKR: Secure and Testable Scan Design through Test Key Randomization.</title><venue>Asian Test Symposium</venue><pages>60-65</pages><year>2011</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/ats/RazzaqSS11</key><doi>10.1109/ATS.2011.85</doi><ee>https://doi.org/10.1109/ATS.2011.85</ee><url>https://dblp.org/rec/conf/ats/RazzaqSS11</url></info>
<url>URL#6173626</url>
</hit>
<hit score="3" id="6173645">
<info><authors><author pid="29/7786-1">Steffen Zeidler 0001</author><author pid="36/7787">Christoph Wolf</author><author pid="33/1954">Milos Krstic</author><author pid="74/1883">Frank Vater</author><author pid="57/3855">Rolf Kraemer</author></authors><title>Design of a Test Processor for Asynchronous Chip Test.</title><venue>Asian Test Symposium</venue><pages>244-250</pages><year>2011</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/ats/ZeidlerWKVK11</key><doi>10.1109/ATS.2011.17</doi><ee>https://doi.org/10.1109/ATS.2011.17</ee><url>https://dblp.org/rec/conf/ats/ZeidlerWKVK11</url></info>
<url>URL#6173645</url>
</hit>
<hit score="3" id="6201945">
<info><authors><author pid="93/4641">Beatriz Pérez Lamancha</author><author pid="97/7092">Pedro Reales Mateo</author><author pid="p/MPolo">Macario Polo</author><author pid="21/1408">Danilo Caivano</author></authors><title>Model-driven Testing - Transformations from Test Models to Test Code.</title><venue>ENASE</venue><pages>121-130</pages><year>2011</year><type>Conference and Workshop Papers</type><access>unavailable</access><key>conf/enase/LamanchaMPC11</key><url>https://dblp.org/rec/conf/enase/LamanchaMPC11</url></info>
<url>URL#6201945</url>
</hit>
<hit score="3" id="6294166">
<info><authors><author pid="p/IrithPomeranz">Irith Pomeranz</author></authors><title>Static test compaction for delay fault test sets consisting of broadside and skewed-load tests.</title><venue>VTS</venue><pages>84-89</pages><year>2011</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/vts/Pomeranz11</key><doi>10.1109/VTS.2011.5783760</doi><ee>https://doi.org/10.1109/VTS.2011.5783760</ee><url>https://dblp.org/rec/conf/vts/Pomeranz11</url></info>
<url>URL#6294166</url>
</hit>
<hit score="3" id="6294181">
<info><authors><author pid="36/3514">Yasuhiro Takahashi</author><author pid="47/4428">Akinori Maeda</author></authors><title>Multi Domain Test: Novel test strategy to reduce the Cost of Test.</title><venue>VTS</venue><pages>303-308</pages><year>2011</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/vts/TakahashiM11</key><doi>10.1109/VTS.2011.5783738</doi><ee>https://doi.org/10.1109/VTS.2011.5783738</ee><url>https://dblp.org/rec/conf/vts/TakahashiM11</url></info>
<url>URL#6294181</url>
</hit>
<hit score="3" id="6302186">
<info><authors><author pid="62/3882">Antti Huima</author></authors><title>Behavioral System Models versus Models of Testing Strategies in Functional Test Generation.</title><venue>Model-Based Testing for Embedded Systems</venue><year>2011</year><type>Parts in Books or Collections</type><access>closed</access><key>books/tf/11/Huima11</key><doi>10.1201/B11321-3</doi><ee>https://doi.org/10.1201/b11321-3</ee><url>https://dblp.org/rec/books/tf/11/Huima11</url></info>
<url>URL#6302186</url>
</hit>
<hit score="3" id="6302188">
<info><authors><author pid="74/6318">Stephen P. Masticola</author><author pid="96/3497">Michael Gall</author></authors><title>Test Framework Architectures for Model-Based Embedded System Testing.</title><venue>Model-Based Testing for Embedded Systems</venue><year>2011</year><type>Parts in Books or Collections</type><access>closed</access><key>books/tf/11/MasticolaG11</key><doi>10.1201/B11321-4</doi><ee>https://doi.org/10.1201/b11321-4</ee><url>https://dblp.org/rec/books/tf/11/MasticolaG11</url></info>
<url>URL#6302188</url>
</hit>
<hit score="3" id="6321516">
<info><authors><author pid="12/4496">Sebastian Benz</author></authors><title>Generating Tests for Feature Interaction (Systematischer Test von Funktionsinteraktionen mittels Testfallgenerierung)</title><year>2010</year><type>Books and Theses</type><access>closed</access><key>phd/de/Benz10</key><ee>https://mediatum.ub.tum.de/805656</ee><url>https://dblp.org/rec/phd/de/Benz10</url></info>
<url>URL#6321516</url>
</hit>
<hit score="3" id="6323401">
<info><authors><author pid="182/7928">Fassely Doumbia</author></authors><title>Contribution à l&apos;analyse de testabilité des systèmes réactifs temps-réel : Aide à la validation et à la vérification de systèmes. (Contribution to the testability analysis of reactive real-time systems: supporting systems validation and verification).</title><year>2010</year><type>Books and Theses</type><access>open</access><key>phd/hal/Doumbia10</key><ee>https://tel.archives-ouvertes.fr/tel-00481072</ee><url>https://dblp.org/rec/phd/hal/Doumbia10</url></info>
<url>URL#6323401</url>
</hit>
<hit score="3" id="6340925">
<info><authors><author pid="28/504">Wolfgang Kössler</author></authors><title>Max-type rank tests, U-tests, and adaptive tests for the two-sample location problem - An asymptotic power study.</title><venue>Comput. Stat. Data Anal.</venue><volume>54</volume><number>9</number><pages>2053-2065</pages><year>2010</year><type>Journal Articles</type><access>closed</access><key>journals/csda/Kossler10</key><doi>10.1016/J.CSDA.2010.03.014</doi><ee>https://doi.org/10.1016/j.csda.2010.03.014</ee><url>https://dblp.org/rec/journals/csda/Kossler10</url></info>
<url>URL#6340925</url>
</hit>
<hit score="3" id="6343680">
<info><authors><author pid="55/6396-1">Scott Davidson 0001</author></authors><title>About the power problem [review of &quot;Power-Aware Testing and Test Strategies for Low Power Devices&quot; (Girard, P., Eds., et.; 2010)].</title><venue>IEEE Des. Test Comput.</venue><volume>27</volume><number>6</number><pages>72-73</pages><year>2010</year><type>Journal Articles</type><access>closed</access><key>journals/dt/Davidson10a</key><doi>10.1109/MDT.2010.122</doi><ee>https://doi.org/10.1109/MDT.2010.122</ee><url>https://dblp.org/rec/journals/dt/Davidson10a</url></info>
<url>URL#6343680</url>
</hit>
<hit score="3" id="6348237">
<info><authors><author pid="45/3706">Ahmad A. Al-Yamani</author><author pid="m/EdwardJMcCluskey">Edward J. McCluskey</author></authors><title>Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns.</title><venue>J. Electron. Test.</venue><volume>26</volume><number>5</number><pages>513-521</pages><year>2010</year><type>Journal Articles</type><access>closed</access><key>journals/et/Al-YamaniM10</key><doi>10.1007/S10836-010-5172-9</doi><ee>https://doi.org/10.1007/s10836-010-5172-9</ee><url>https://dblp.org/rec/journals/et/Al-YamaniM10</url></info>
<url>URL#6348237</url>
</hit>
<hit score="3" id="6348269">
<info><authors><author pid="61/7646">Usha Sandeep Mehta</author><author pid="88/8324">Kankar S. Dasgupta</author><author pid="28/8325">Nirnjan M. Devashrayee</author></authors><title>Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead.</title><venue>J. Electron. Test.</venue><volume>26</volume><number>6</number><pages>679-688</pages><year>2010</year><type>Journal Articles</type><access>closed</access><key>journals/et/MehtaDD10</key><doi>10.1007/S10836-010-5183-6</doi><ee>https://doi.org/10.1007/s10836-010-5183-6</ee><url>https://dblp.org/rec/journals/et/MehtaDD10</url></info>
<url>URL#6348269</url>
</hit>
<hit score="3" id="6348273">
<info><authors><author pid="04/6660">Kazuteru Namba</author><author pid="88/6836">Hideo Ito</author></authors><title>Chiba Scan Delay Fault Testing with Short Test Application Time.</title><venue>J. Electron. Test.</venue><volume>26</volume><number>6</number><pages>667-677</pages><year>2010</year><type>Journal Articles</type><access>closed</access><key>journals/et/NambaI10</key><doi>10.1007/S10836-010-5177-4</doi><ee>https://doi.org/10.1007/s10836-010-5177-4</ee><url>https://dblp.org/rec/journals/et/NambaI10</url></info>
<url>URL#6348273</url>
</hit>
<hit score="3" id="6351849">
<info><authors><author pid="59/7080">Shaochong Lei</author><author pid="78/6727">Zhen Wang</author><author pid="52/8788-2">Zeye Liu 0002</author><author pid="54/6821">Feng Liang</author></authors><title>A unified solution to reduce test power and test volume for Test-per-scan schemes.</title><venue>IEICE Electron. Express</venue><volume>7</volume><number>18</number><pages>1364-1369</pages><year>2010</year><type>Journal Articles</type><access>open</access><key>journals/ieiceee/LeiWLL10a</key><doi>10.1587/ELEX.7.1364</doi><ee>https://doi.org/10.1587/elex.7.1364</ee><url>https://dblp.org/rec/journals/ieiceee/LeiWLL10a</url></info>
<url>URL#6351849</url>
</hit>
<hit score="3" id="6353741">
<info><authors><author pid="80/534">Wang-Dauh Tseng</author><author pid="92/3489">Lung-Jen Lee</author><author pid="27/1501">Rung-Bin Lin</author></authors><title>Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction.</title><venue>IET Comput. Digit. Tech.</venue><volume>4</volume><number>4</number><pages>317-324</pages><year>2010</year><type>Journal Articles</type><access>closed</access><key>journals/iet-cdt/TsengLL10</key><doi>10.1049/IET-CDT.2009.0092</doi><ee>https://doi.org/10.1049/iet-cdt.2009.0092</ee><url>https://dblp.org/rec/journals/iet-cdt/TsengLL10</url></info>
<url>URL#6353741</url>
</hit>
<hit score="3" id="6376986">
<info><authors><author pid="46/8357">Chris Andrzejczak</author><author pid="17/1780">Dahai Liu</author></authors><title>The effect of testing location on usability testing performance, participant stress levels, and subjective testing experience.</title><venue>J. Syst. Softw.</venue><volume>83</volume><number>7</number><pages>1258-1266</pages><year>2010</year><type>Journal Articles</type><access>closed</access><key>journals/jss/AndrzejczakL10</key><doi>10.1016/J.JSS.2010.01.052</doi><ee>https://doi.org/10.1016/j.jss.2010.01.052</ee><url>https://dblp.org/rec/journals/jss/AndrzejczakL10</url></info>
<url>URL#6376986</url>
</hit>
<hit score="3" id="6395366">
<info><authors><author pid="c/WingKwonChan">W. K. Chan 0001</author><author pid="42/5393">Jeffrey C. F. Ho</author><author pid="t/THTse">T. H. Tse</author></authors><title>Finding failures from passed test cases: improving the pattern classification approach to the testing of mesh simplification programs.</title><venue>Softw. Test. Verification Reliab.</venue><volume>20</volume><number>2</number><pages>89-120</pages><year>2010</year><type>Journal Articles</type><access>closed</access><key>journals/stvr/ChanHT10</key><doi>10.1002/STVR.408</doi><ee>https://doi.org/10.1002/stvr.408</ee><url>https://dblp.org/rec/journals/stvr/ChanHT10</url></info>
<url>URL#6395366</url>
</hit>
<hit score="3" id="6419910">
<info><authors><author pid="97/374-7">Xiang Fu 0007</author><author pid="70/576-1">Huawei Li 0001</author><author pid="37/5372-1">Xiaowei Li 0001</author></authors><title>On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing.</title><venue>Asian Test Symposium</venue><pages>45-48</pages><year>2010</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/ats/FuLL10</key><doi>10.1109/ATS.2010.17</doi><ee>https://doi.org/10.1109/ATS.2010.17</ee><url>https://dblp.org/rec/conf/ats/FuLL10</url></info>
<url>URL#6419910</url>
</hit>
<hit score="3" id="6419920">
<info><authors><author pid="64/9056">Masashi Ishikawa</author><author pid="00/2646">Hiroyuki Yotsuyanagi</author><author pid="09/5520">Masaki Hashizume</author></authors><title>Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code.</title><venue>Asian Test Symposium</venue><pages>163-166</pages><year>2010</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/ats/IshikawaYH10</key><doi>10.1109/ATS.2010.37</doi><ee>https://doi.org/10.1109/ATS.2010.37</ee><url>https://dblp.org/rec/conf/ats/IshikawaYH10</url></info>
<url>URL#6419920</url>
</hit>
<hit score="3" id="6419944">
<info><authors><author pid="23/1778">Joonsung Park</author><author pid="05/67">Jae Wook Lee</author><author pid="73/3431">Jaeyong Chung</author><author pid="37/8375">Kihyuk Han</author><author pid="a/JacobAAbraham">Jacob A. Abraham</author><author pid="76/8337">Eonjo Byun</author><author pid="13/8338">Cheol-Jong Woo</author><author pid="41/8375">Sejang Oh</author></authors><title>At-speed Test of High-Speed DUT Using Built-Off Test Interface.</title><venue>Asian Test Symposium</venue><pages>269-274</pages><year>2010</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/ats/ParkLCHABWO10</key><doi>10.1109/ATS.2010.54</doi><ee>https://doi.org/10.1109/ATS.2010.54</ee><url>https://dblp.org/rec/conf/ats/ParkLCHABWO10</url></info>
<url>URL#6419944</url>
</hit>
<hit score="3" id="6419953">
<info><authors><author pid="74/8337">Xiaoqin Sheng</author><author pid="19/6515">Hans G. Kerkhoff</author></authors><title>The Test Ability of an Adaptive Pulse Wave for ADC Testing.</title><venue>Asian Test Symposium</venue><pages>289-294</pages><year>2010</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/ats/ShengK10</key><doi>10.1109/ATS.2010.56</doi><ee>https://doi.org/10.1109/ATS.2010.56</ee><url>https://dblp.org/rec/conf/ats/ShengK10</url></info>
<url>URL#6419953</url>
</hit>
<hit score="3" id="6419960">
<info><authors><author pid="00/4210">Tung-Hua Yeh</author><author pid="08/6019">Sying-Jyan Wang</author></authors><title>Thermal Safe High Level Test Synthesis for Hierarchical Testability.</title><venue>Asian Test Symposium</venue><pages>337-342</pages><year>2010</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/ats/YehW10</key><doi>10.1109/ATS.2010.64</doi><ee>https://doi.org/10.1109/ATS.2010.64</ee><url>https://dblp.org/rec/conf/ats/YehW10</url></info>
<url>URL#6419960</url>
</hit>
<hit score="3" id="6443310">
<info><authors><author pid="68/4231">Michiko Inoue</author><author pid="16/8338">Akira Taketani</author><author pid="56/1496">Tomokazu Yoneda</author><author pid="90/8122">Hiroshi Iwata</author><author pid="64/1146">Hideo Fujiwara</author></authors><title>Test pattern selection to optimize delay test quality with a limited size of test set.</title><venue>ETS</venue><pages>260</pages><year>2010</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/ets/InoueTYIF10</key><doi>10.1109/ETSYM.2010.5512733</doi><ee>https://doi.org/10.1109/ETSYM.2010.5512733</ee><url>https://dblp.org/rec/conf/ets/InoueTYIF10</url></info>
<url>URL#6443310</url>
</hit>
<hit score="3" id="6475515">
<info><authors><author pid="23/2889">Fabrice Bouquet</author><author pid="30/7856">Pierre-Christophe Bué</author><author pid="88/4752">Jacques Julliand</author><author pid="31/3727">Pierre-Alain Masson</author></authors><title>Test Generation Based on Abstraction and Test Purposes to Complement Structural Tests.</title><venue>ICST Workshops</venue><pages>54-61</pages><year>2010</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/icst/BouquetBJM10</key><doi>10.1109/ICSTW.2010.47</doi><ee>https://doi.org/10.1109/ICSTW.2010.47</ee><url>https://dblp.org/rec/conf/icst/BouquetBJM10</url></info>
<url>URL#6475515</url>
</hit>
<hit score="3" id="6536830">
<info><authors><author pid="58/6236">Ido Ben-Eliezer</author><author pid="42/209">Tali Kaufman</author><author pid="09/3445">Michael Krivelevich</author><author pid="85/4800">Dana Ron</author></authors><title>Comparing the Strength of Query Types in Property Testing: The Case of Testing k-Colorability.</title><venue>Property Testing</venue><pages>253-259</pages><year>2010</year><type>Parts in Books or Collections</type><access>closed</access><key>conf/propertytesting/Ben-EliezerKKR10</key><doi>10.1007/978-3-642-16367-8_17</doi><ee>https://doi.org/10.1007/978-3-642-16367-8_17</ee><url>https://dblp.org/rec/conf/propertytesting/Ben-EliezerKKR10</url></info>
<url>URL#6536830</url>
</hit>
<hit score="3" id="6541754">
<info><authors><author pid="03/4157">Bruno Legeard</author></authors><title>Model-based Testing: Next Generation Functional Software Testing.</title><venue>Practical Software Testing - Tool Automation and Human Factors</venue><year>2010</year><type>Informal and Other Publications</type><access>open</access><key>conf/dagstuhl/Legeard10</key><ee>http://drops.dagstuhl.de/opus/volltexte/2010/2620/</ee><url>https://dblp.org/rec/conf/dagstuhl/Legeard10</url></info>
<url>URL#6541754</url>
</hit>
<hit score="3" id="6564221">
<info><authors><author pid="91/8945">P. C. Jha 0001</author><author pid="26/2002">Deepali Gupta</author><author pid="46/999-11">Bo Yang 0011</author><author pid="14/10037">P. K. Kapur 0001</author></authors><title>Optimal testing resource allocation during module testing considering cost, testing effort and reliability.</title><venue>Comput. Ind. Eng.</venue><volume>57</volume><number>3</number><pages>1122-1130</pages><year>2009</year><type>Journal Articles</type><access>closed</access><key>journals/candie/JhaGYK09</key><doi>10.1016/J.CIE.2009.05.001</doi><ee>https://doi.org/10.1016/j.cie.2009.05.001</ee><url>https://dblp.org/rec/journals/candie/JhaGYK09</url></info>
<url>URL#6564221</url>
</hit>
<hit score="3" id="6565973">
<info><authors><author pid="87/9150">Jane Carstairs</author><author pid="66/9148">Brett Myors</author></authors><title>Internet testing: A natural experiment reveals test score inflation on a high-stakes, unproctored cognitive test.</title><venue>Comput. Hum. Behav.</venue><volume>25</volume><number>3</number><pages>738-742</pages><year>2009</year><type>Journal Articles</type><access>closed</access><key>journals/chb/CarstairsM09</key><doi>10.1016/J.CHB.2009.01.011</doi><ee>https://doi.org/10.1016/j.chb.2009.01.011</ee><url>https://dblp.org/rec/journals/chb/CarstairsM09</url></info>
<url>URL#6565973</url>
</hit>
<hit score="3" id="6573947">
<info><authors><author pid="55/6396-1">Scott Davidson 0001</author></authors><title>A second course on testing [review of System on Chip Test Architectures (Wang, L.-T et al., Eds.; 2007)].</title><venue>IEEE Des. Test Comput.</venue><volume>26</volume><number>1</number><pages>98-101</pages><year>2009</year><type>Journal Articles</type><access>closed</access><key>journals/dt/Davidson09</key><doi>10.1109/MDT.2009.2</doi><ee>https://doi.org/10.1109/MDT.2009.2</ee><url>https://dblp.org/rec/journals/dt/Davidson09</url></info>
<url>URL#6573947</url>
</hit>
<hit score="3" id="6573948">
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<url>URL#6573948</url>
</hit>
<hit score="3" id="6573983">
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<url>URL#6573983</url>
</hit>
<hit score="3" id="6578051">
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<url>URL#6578051</url>
</hit>
<hit score="3" id="6578634">
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<url>URL#6578634</url>
</hit>
<hit score="3" id="6583304">
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<url>URL#6583304</url>
</hit>
<hit score="3" id="6592670">
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<url>URL#6592670</url>
</hit>
<hit score="3" id="6592802">
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<hit score="3" id="6609415">
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<url>URL#6609415</url>
</hit>
<hit score="3" id="6621599">
<info><authors><author pid="65/4952">Ian Gilchrist</author></authors><title>Software testing - testing across the entire software development lifecycle. By Gerald D Everett &amp; Raymond McLeod Jr. Published by IEEE Press and Wiley Interscience, Hoboken, NJ, USA ISBN: 978-0-471-79371-7, 260 pages.</title><venue>Softw. Test. Verification Reliab.</venue><volume>19</volume><number>1</number><pages>85-86</pages><year>2009</year><type>Journal Articles</type><access>closed</access><key>journals/stvr/Gilchrist09</key><doi>10.1002/STVR.384</doi><ee>https://doi.org/10.1002/stvr.384</ee><url>https://dblp.org/rec/journals/stvr/Gilchrist09</url></info>
<url>URL#6621599</url>
</hit>
<hit score="3" id="6621601">
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<url>URL#6621601</url>
</hit>
<hit score="3" id="6623462">
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<url>URL#6623462</url>
</hit>
<hit score="3" id="6623705">
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<url>URL#6623705</url>
</hit>
<hit score="3" id="6643858">
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</hit>
<hit score="3" id="6645455">
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<url>URL#6645462</url>
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<url>URL#6645468</url>
</hit>
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<info><authors><author pid="56/3227">Michael S. Hsiao</author><author pid="20/2219">Mainak Banga</author></authors><title>Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application Time.</title><venue>Asian Test Symposium</venue><pages>225-230</pages><year>2009</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/ats/HsiaoB09</key><doi>10.1109/ATS.2009.17</doi><ee>https://doi.org/10.1109/ATS.2009.17</ee><url>https://dblp.org/rec/conf/ats/HsiaoB09</url></info>
<url>URL#6645475</url>
</hit>
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<url>URL#6645492</url>
</hit>
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<url>URL#6645494</url>
</hit>
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<url>URL#6645495</url>
</hit>
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<url>URL#6645497</url>
</hit>
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<info><authors><author pid="44/6464">Anis Uzzaman</author></authors><title>Is Low Power Testing Necessary? What does the Test Industry Truly Need?.</title><venue>Asian Test Symposium</venue><pages>215-216</pages><year>2009</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/ats/Uzzaman09</key><doi>10.1109/ATS.2009.91</doi><ee>https://doi.org/10.1109/ATS.2009.91</ee><url>https://dblp.org/rec/conf/ats/Uzzaman09</url></info>
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</hit>
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</hit>
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</hit>
<hit score="3" id="6800685">
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<url>URL#6800685</url>
</hit>
<hit score="3" id="6800706">
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<url>URL#6800706</url>
</hit>
<hit score="3" id="6839574">
<info><authors><author pid="67/396">Claus Gittinger</author></authors><title>Modellbasierte Testentwicklung - Verwendung von Aktivitätsdiagrammen als Testspezifikation im expecco-Testsystem.</title><venue>Softwaretechnik-Trends</venue><volume>28</volume><number>1</number><year>2008</year><type>Journal Articles</type><access>unavailable</access><key>journals/stt/Gittinger08</key><ee>http://pi.informatik.uni-siegen.de/stt/28_1/01_Fachgruppenberichte/TAV/TAV26P7GittingerKurz.pdf</ee><url>https://dblp.org/rec/journals/stt/Gittinger08</url></info>
<url>URL#6839574</url>
</hit>
<hit score="3" id="6839588">
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<url>URL#6839588</url>
</hit>
<hit score="3" id="6839656">
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<url>URL#6839656</url>
</hit>
<hit score="3" id="6863181">
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<url>URL#6863181</url>
</hit>
<hit score="3" id="6879930">
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<url>URL#6879930</url>
</hit>
<hit score="3" id="6881112">
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<url>URL#6881112</url>
</hit>
<hit score="3" id="6889633">
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<url>URL#6889633</url>
</hit>
<hit score="3" id="6889635">
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<url>URL#6889635</url>
</hit>
<hit score="3" id="6892422">
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</hit>
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</hit>
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</hit>
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<url>URL#7004285</url>
</hit>
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<url>URL#7004294</url>
</hit>
<hit score="3" id="7004318">
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</hit>
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</hit>
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</hit>
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<url>URL#7062763</url>
</hit>
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<url>URL#7062770</url>
</hit>
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</hit>
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</hit>
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</hit>
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</hit>
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</hit>
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<url>URL#7166024</url>
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<url>URL#7192741</url>
</hit>
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<url>URL#7192745</url>
</hit>
<hit score="3" id="7192747">
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</hit>
<hit score="3" id="7226500">
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<url>URL#7226542</url>
</hit>
<hit score="3" id="7226624">
<info><authors><author pid="h/RobertMHierons">Robert M. Hierons</author></authors><title>Software Testing Foundations: A Study Guide for the Certified Tester Exam. By Andreas Spillner, Tilo Linz and Hans Schaefer. Published by dpunkt.verlag, Heidelberg, Germany, 2006, ISBN: 3-89864-363-8, pp 266.</title><venue>Softw. Test. Verification Reliab.</venue><volume>16</volume><number>4</number><pages>289-290</pages><year>2006</year><type>Journal Articles</type><access>closed</access><key>journals/stvr/Hierons06a</key><doi>10.1002/STVR.358</doi><ee>https://doi.org/10.1002/stvr.358</ee><url>https://dblp.org/rec/journals/stvr/Hierons06a</url></info>
<url>URL#7226624</url>
</hit>
<hit score="3" id="7248058">
<info><authors><author pid="00/6938">Juergen Grossmann</author><author pid="14/322">Ines Fey</author><author pid="24/160">Alexander Krupp</author><author pid="07/5828">Mirko Conrad</author><author pid="33/22">Christian Wewetzer</author><author pid="m/WMuller3">Wolfgang Müller 0003</author></authors><title>TestML - A Test Exchange Language for Model-Based Testing of Embedded Software.</title><venue>ASWSD</venue><pages>98-117</pages><year>2006</year><type>Conference and Workshop Papers</type><access>closed</access><key>conf/aswsd/GrossmannFKCWM06</key><doi>10.1007/978-3-540-70930-5_7</doi><ee>https://doi.org/10.1007/978-3-540-70930-5_7</ee><url>https://dblp.org/rec/conf/aswsd/GrossmannFKCWM06</url></info>
<url>URL#7248058</url>
</hit>
</hits>
</result>
