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Modelling and Simulation of the Propagation of P-SV Seismic Waves from Earthquakes: Application to Deep Earthquakes in Acre, Brazil
Authors:
Pedro Huan Moreira,
Andina Alay Lerma,
Eliandro Rodrigues Cirilo,
Neyva Maria Lopes Romeiro,
Waldemir Lima Dos Santos,
Paulo Laerte Natti
Abstract:
Brazil is located in the central-eastern portion of the South American Plate, meaning that the country mostly experiences low-intensity seismic activity within its territory. However, some geological faults in this region have generated intense earthquakes. In this context, we intend to describe a recent earthquake of magnitude around 6.5 M_b that occurred at a depth of approximately 600 km in the…
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Brazil is located in the central-eastern portion of the South American Plate, meaning that the country mostly experiences low-intensity seismic activity within its territory. However, some geological faults in this region have generated intense earthquakes. In this context, we intend to describe a recent earthquake of magnitude around 6.5 M_b that occurred at a depth of approximately 600 km in the state of Acre, Brazil. In this work, we modeled the propagation of P-SV seismic waves using a two-dimensional system of partial differential equations (PDEs) in a two-dimensional vertical rectangular domain. The source is modeled by a Gaussian pulse function. The initial quiescence condition and Neumann boundary conditions are used. The PDE system is discretized by the finite difference method (FDM) and solved by the Gauss-Seidel method (GSM). The numerical simulations obtained describe the propagation of attenuated seismic waves in multiple geological layers, simulating intense and deep earthquakes in Acre. We used the propagation of perfect seismic waves to validate the model. The results include images of the simulations and theoretical seismograms simulating the vertical and horizontal displacement in the epicenter region and 200 km east and west of the epicenter.
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Submitted 6 January, 2026;
originally announced January 2026.
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Aerodynamic Influence Over Leading and Pursuing Motorcycles Equipped With Downforce-Generation Wings
Authors:
Braulio Gutierrez Pimenta,
Luís Paulo de Queiroz Moreira,
Adriano Possebon Rosa,
Roberto Francisco Bobenrieth Miserda
Abstract:
The aerodynamic influence of a wing-equipped motorcycle on a pursuing motorcycle presents critical implications for stability and performance. This study investigates the induced flow dynamics, characterized by a turbulent and complex wake that significantly affects the aerodynamic forces and moments experienced by the following motorcycle. The presence of aerodynamic appendices on the leading mot…
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The aerodynamic influence of a wing-equipped motorcycle on a pursuing motorcycle presents critical implications for stability and performance. This study investigates the induced flow dynamics, characterized by a turbulent and complex wake that significantly affects the aerodynamic forces and moments experienced by the following motorcycle. The presence of aerodynamic appendices on the leading motorcycle intensifies these effects, generating coherent wingtip vortices that propagate downstream-a typical behavior of lift-generating devices. In this work, numerical simulations reveal that the aerodynamic consequences vary with the relative positioning of the pursuing motorcycle. A lateral offset can reduce wheelie tendencies due to beneficial flow interactions, while lateral alignment and longitudinal positioning variation may exacerbate negative aerodynamic impacts, compromising stability. Contrary to initial expectations, the simulations in this work demonstrate that the turbulent wake and the coherent vortex pair influence the pursuing motorcycle's behavior independently, persisting across all tested relative distances. While the turbulent wake usually creates a low-pressure region that facilitates drafting, the presence of coherent vortices reduces this advantage by introducing additional lift through the upwash velocity component. Conversely, specific lateral deviations can lessen wheelie effects, with downwash becoming the dominant flow component. Although difficult to be removed promptly due to being part of the overall high performance motorcycle design, it is suggested that the downforce generating aerodynamic appendices removal should be considered by the motorcycling competition governing bodies to provide better safety and racing conditions at all categories that make use of it.
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Submitted 6 November, 2024;
originally announced November 2024.
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The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector
Authors:
L. Zhang,
D. Gong,
T. Liu,
C. Chen,
B. Deng,
S. Hou,
G. Huang,
X. Huang,
C. Liu,
P. Moreira,
Q. Sun,
X. Sun,
S. Kulis,
J. Ye,
W. Zhang
Abstract:
This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cable…
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This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals from lpGBT before sending them to RD53B through the same cables. No Single-Event Upset (SEU) is observed in any tested channels of GBCR2 in a 400 MeV proton beam. The extrapolated bit error rate for the future HL-LHC application is below 8*10^(-16), significantly below the specified BER criterion. GBCR3 is designed to improve the immunity to single-event-upset by applying the Triple Modular Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3 have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each receiver channel of GBCR3 consumes 75% more power than that of GBCR2.
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Submitted 30 January, 2023;
originally announced January 2023.
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A 20 Gbps PAM4 Data Transmitter ASIC for Particle Physics Experiments
Authors:
L. Zhang,
E. M. Cruda,
C-P. Chao,
S-W. Chen,
B. Deng,
R. Francisco,
D. Gong,
D. Guo,
S. Hou,
G. Huang,
X. Huang,
S. Kulis,
C-Y. Li,
C. Liu,
E. R. Liu,
T. Liu,
P. Moreira,
J. Prinzie,
H. Sun,
Q. Sun,
X. Sun,
G. Wong,
D. Yang,
J. Ye,
W. Zhang
Abstract:
We present the design and test results of a novel data transmitter ASIC operating up to 20.48 Gbps with 4-level Pulse-Amplitude-Modulation (PAM4) for particle physics experiments. This ASIC, named GBS20, is fabricated in a 65 nm CMOS technology. Two serializers share a 5.12 GHz Phase Locked Loop (PLL) clock. The outputs from the serializers are combined into a PAM4 signal that directly drives a Ve…
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We present the design and test results of a novel data transmitter ASIC operating up to 20.48 Gbps with 4-level Pulse-Amplitude-Modulation (PAM4) for particle physics experiments. This ASIC, named GBS20, is fabricated in a 65 nm CMOS technology. Two serializers share a 5.12 GHz Phase Locked Loop (PLL) clock. The outputs from the serializers are combined into a PAM4 signal that directly drives a Vertical-Cavity-Surface-Emitting-Laser (VCSEL). The input data channels, each at 1.28 Gbps, are scrambled with an internal 27-1 Pseudo-Random Binary Sequence (PRBS), which also serves as a frame aligner. GBS20 is tested to work at 10.24 and 20.48 Gbps with a VCSEL-based Transmitter-Optical-Subassembly (TOSA). The power consumption of GBS20 is below 238 mW and reduced to 164 mW in the low-power mode.
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Submitted 7 February, 2022;
originally announced February 2022.
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QTIA, a 2.5 or 10 Gbps 4-Channel Array Optical Receiver ASIC in a 65 nm CMOS Technology
Authors:
H. Sun,
X. Huang,
C. -P. Chao,
S. -W. Chen,
B. Deng,
D. Gong,
S. Hou,
G. Huang,
S. Kulis,
C. -Y. Li,
C. Liu,
T. Liu,
P. Moreira,
Q. Sun,
J. Ye,
L. Zhang,
W. Zhang
Abstract:
The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is…
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The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, which is especially important to mitigate radiation effects on the photodiodes. The circuit functions of QTIA successfully passed the lab tests with GaAs photodiodes.
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Submitted 11 February, 2022; v1 submitted 24 October, 2021;
originally announced October 2021.
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A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip
Authors:
H. Sun,
Q. Sun,
S. Biereigel,
R. Francisco,
D. Gong,
G. Huang,
X. Huang,
S. Kulis,
P. Leroux,
C. Liu,
T. Liu,
T. Liu,
P. Moreira,
J. Prinzie,
J. Wu,
J. Ye,
L. Zhang,
W. Zhang
Abstract:
We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR…
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We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear energy transfer (LET) from 1.3 to 62.5 MeV*cm^2/mg.
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Submitted 11 February, 2022; v1 submitted 24 October, 2021;
originally announced October 2021.
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A novel quad-channel 10 Gbps CMOS VCSEL array driver with integrated charge pumps
Authors:
X. Huang,
D. Gong,
D. Guo,
S. Hou,
G. Huang,
S. Kulis,
C. Liu,
T. Liu,
P. Moreira,
A. Sánchez Rodríguez,
H. Sun,
Q. Sun,
J. Troska,
L. Xiao,
L. Zhang,
W. Zhang,
J. Ye
Abstract:
We present a novel design and the test results of a 4-channel driver for an array of Vertical-Cavity Surface-Emitting Lasers (VCSELs). This ASIC, named cpVLAD and fabricated in a 65 nm CMOS technology, has on-chip charge pumps and is for data rates up to 10 Gbps per channel. The charge pumps are implemented to address the issue of voltage margin of the VCSEL driving stage in the applications under…
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We present a novel design and the test results of a 4-channel driver for an array of Vertical-Cavity Surface-Emitting Lasers (VCSELs). This ASIC, named cpVLAD and fabricated in a 65 nm CMOS technology, has on-chip charge pumps and is for data rates up to 10 Gbps per channel. The charge pumps are implemented to address the issue of voltage margin of the VCSEL driving stage in the applications under low temperature and harsh radiation environment. Test results indicate that cpVLAD is capable of driving VCSELs with forward voltages of up to 2.8 V using 1.2 V and 2.5 V power supplies with a power consumption of 94 mW/channel.
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Submitted 31 October, 2020;
originally announced November 2020.
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A 4-Channel 10-Gbps/ch CMOS VCSEL Array Driver with on-chip Charge-pumps
Authors:
X. Huang,
D. Gong,
Q. Sun,
C. Chen,
D. Guo,
S. Hou,
G. Huang,
S. Kulis,
C. Liu,
T. Liu,
P. Moreira,
A. Sánchez Rodríguez,
H. Sun,
J. Troska,
L. Xiao,
L. Zhang,
W. Zhang,
J. Ye
Abstract:
We present the design and test results of a 4-channel 10-Gbps/ch Vertical-Cavity Surface-Emitting Laser array driver, the cpVLAD. With on-chip charge-pumps to extend the biasing headroom for the VCSELs needed for low temperature operation and mitigation of the radiation effects. The cpVLAD was fabricated in a 65-nm CMOS technology. The test results show that the cpVLAD is capable of driving VCSELs…
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We present the design and test results of a 4-channel 10-Gbps/ch Vertical-Cavity Surface-Emitting Laser array driver, the cpVLAD. With on-chip charge-pumps to extend the biasing headroom for the VCSELs needed for low temperature operation and mitigation of the radiation effects. The cpVLAD was fabricated in a 65-nm CMOS technology. The test results show that the cpVLAD is capable of driving VCSELs with forward bias voltages as high as 2.8 V from a 2.5 V power supply. The power consumption of the cpVLAD is 94 mW/ch.
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Submitted 13 September, 2020;
originally announced September 2020.
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A gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade
Authors:
C. Chen,
V. Wallangen,
D. Gong,
C. Grace,
Q. Sun,
D. Guo,
G. Huang,
S. Kulis,
P. Leroux,
C. Liu,
T. Liu,
P. Moreira,
J. Prinzie,
L. Xiao,
J. Ye
Abstract:
This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver channels and a downstream transmitter channel. Each upstream channel operates at 5.12 Gbps, while the downstream channel operates at 2.56 Gbps. In each upstream cha…
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This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver channels and a downstream transmitter channel. Each upstream channel operates at 5.12 Gbps, while the downstream channel operates at 2.56 Gbps. In each upstream channel, GBCR equalizes a signal received through a 5-meter 34-American Wire Gauge (AWG) twin-axial cable, retimes the data with a recovered clock, and drives an optical transmitter. In the downstream channel, GBCR receives the data from an optical receiver and drives the same type of cable as the upstream channels. The output jitter of an upstream channel is 26.5 ps and the jitter of the downstream channel after the cable is 33.5 ps. Each upstream channel consumes 78 mW and each downstream channel consumes 27 mW. Simulation results of the upstream test channel suggest that a significant jitter reduction could be achieved with minimally increased power consumption by using a Feed Forward Equalizer (FFE) + Decision Feedback Equalization (DFE) in addition to the linear equalization of the baseline channel. GBCR is designed in a 65-nm CMOS technology.
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Submitted 13 September, 2020;
originally announced September 2020.
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Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade
Authors:
C. Chen,
D. Gong,
D. Guo,
G. Huang,
X. Huang,
S. Kulis,
P. Leroux,
C. Liu,
T. Liu,
P. Moreira,
J. Prinzie,
Q. Sun,
P. Wang,
L. Xiao,
J. Ye
Abstract:
We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing throu…
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We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize them, retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.
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Submitted 21 August, 2020;
originally announced August 2020.
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1.28 and 5.12 Gbps multi-channel twinax cable receiver ASICs for the ATLAS Inner Tracker Pixel Detector Upgrade
Authors:
Chufeng Chen,
Datao Gong,
Suen Hou,
Guangming Huang,
Xing Huang,
Szymon Kulis,
Paul Leroux,
Chonghan Liu,
Tiankuan Liu,
Paulo Moreira,
Jefery Prinzie,
Peilong Wang,
Jingbo Ye
Abstract:
We present two prototypes of a gigabit transceiver ASIC, GBCR1 and GBCR2, both designed in a 65-nm CMOS technology for the ATLAS Inner Tracker Pixel Detector readout upgrade.
The first prototype, GBCR1, has four upstream receiver channels and one downstream transmitter channel with pre-emphasis. Each upstream channel receives the data at 5.12 Gbps through a 5 meter AWG34 Twinax cable from an ASI…
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We present two prototypes of a gigabit transceiver ASIC, GBCR1 and GBCR2, both designed in a 65-nm CMOS technology for the ATLAS Inner Tracker Pixel Detector readout upgrade.
The first prototype, GBCR1, has four upstream receiver channels and one downstream transmitter channel with pre-emphasis. Each upstream channel receives the data at 5.12 Gbps through a 5 meter AWG34 Twinax cable from an ASIC driver located on the pixel module and restores the signal from the high frequency loss due to the low mass cable. The signal is retimed by a recovered clock before it is sent to the optical transmitter VTRx+. The downstream driver is designed to transmit the 2.56 Gbps signal from lpGBT to the electronics on the pixel module over the same cable. The peak-peak jitter (throughout the paper jitter is always peak-peak unless specified) of the restored signal is 35.4 ps at the output of GBCR1, and 138 ps for the downstream channel at the cable ends. GBCR1 consumes 318 mW and is tested.
The second prototype, GBCR2, has seven upstream channels and two downstream channels. Each upstream channel works at 1.28 Gbps to recover the data directly from the RD53B ASIC through a 1 meter custom FLEX cable followed by a 6 meter AWG34 Twinax cable. The equalized signal of each upstream channel is retimed by an input 1.28 GHz phase programmable clock. Compared with the signal at the FLEX input, the additional jitter of the equalized signal is about 80 ps when the retiming logic is o . When the retiming logic is on, the jitter is 50 ps at GBCR2 output, assuming the 1.28 GHz retiming clock is from lpGBT. The downstream is designed to transmit the 160 Mbps signal from lpGBT through the same cable connection to RD53B and the jitter is about 157 ps at the cable ends. GBCR2 consumes about 150 mW when the retiming logic is on. This design was submitted in November 2019.
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Submitted 21 August, 2020;
originally announced August 2020.
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Nota Técnica dos Modelos Implementados pelo Coletivo Covid19br para Projeções de Cenários Futuros da Pandemia COVID-19 no Brasil
Authors:
Daniel Severo,
Giuliano Netto Flores Cruz,
Alcides Carlos de Araújo,
André Marques dos Santos,
André Luiz Nunes Martins,
Carolina Ferreira da Silva,
Cristiane Schmitz,
Felipe Brum de Brito Sousa,
Gabriel Domingos de Arruda,
Gabriel Mendes Cabral Gondim,
Giovanna Ferraresso,
Joao Ricardo Vissoci,
Marcel Figueredo S. Figueredo,
Rafael Prudencio Moreira,
Ralf Lima da Costa,
Vito Ribeiro Venturieri,
Diógenes Adriano Rizzoto Justo
Abstract:
This technical note aims to provide a brief introduction to the projection models used by the group to project future scenarios for states and municipalities in real-time, according to the disease's behavior in previous days. However, the parameters can be modified by the user to design customized scenarios. The proposed model begins with the calculation of the basic reproduction number for the st…
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This technical note aims to provide a brief introduction to the projection models used by the group to project future scenarios for states and municipalities in real-time, according to the disease's behavior in previous days. However, the parameters can be modified by the user to design customized scenarios. The proposed model begins with the calculation of the basic reproduction number for the state or municipality based on the incidence of cases in the last 12 days. Once this is done, the epidemiological curve is projected using the SEIR compartmentalized epidemic model, in possession of this curve, part of the newly projected infected enter a simulation model for health systems in queuing theory, aiming to project future occupations and collapses.
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Submitted 25 April, 2020;
originally announced April 2020.
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Quantum equilibration of a model system Porphine
Authors:
Guillermo Albareda,
Arnau Riera,
Miguel Gonzalez,
Josep Maria Bofill,
Iberio de P. R Moreira,
Rosendo Valero,
Ivano Tavernelli
Abstract:
There is a renewed interest in the derivation of statistical mechanics from the dynamics of closed quantum systems. A central part of this program is to understand how far-from-equilibrium closed quantum system can behave as if relaxing to a stable equilibrium. Equilibration dynamics has been traditionally studied with a focus on the so-called quenches of large-scale many-body systems. Alternative…
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There is a renewed interest in the derivation of statistical mechanics from the dynamics of closed quantum systems. A central part of this program is to understand how far-from-equilibrium closed quantum system can behave as if relaxing to a stable equilibrium. Equilibration dynamics has been traditionally studied with a focus on the so-called quenches of large-scale many-body systems. Alternatively, we consider here the equilibration of a molecular model system describing the double proton transfer reaction in porphine. Using numerical simulations, we show that equilibration in this context indeed takes place and does so very rapidly ($\sim \!\! 200$fs) for initial states induced by pump-dump laser pulse control with energies well above the synchronous tunneling barrier.
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Submitted 14 October, 2019;
originally announced October 2019.
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Elastic constants of Ice I$_h$ as described by semi-empirical water models
Authors:
Pedro Augusto Franco Pinheiro Moreira,
Roberto Gomes de Aguiar Veiga,
Maurice de Koning
Abstract:
Using molecular dynamics simulations we compute the elastic constants of ice I$_h$ for a set of 8 frequently used semi-empirical potentials for water, namely the rigid-molecule SPC/E, TIP4P, TIP4P2005, TIP4P/Ice and TIP5P models, the flexible-molecule qTIP4P/Fw and SPC/Fw models and the coarse-grained atomic mW potential. In quantitative terms, the mW description gives values for the individual st…
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Using molecular dynamics simulations we compute the elastic constants of ice I$_h$ for a set of 8 frequently used semi-empirical potentials for water, namely the rigid-molecule SPC/E, TIP4P, TIP4P2005, TIP4P/Ice and TIP5P models, the flexible-molecule qTIP4P/Fw and SPC/Fw models and the coarse-grained atomic mW potential. In quantitative terms, the mW description gives values for the individual stiffness constants that are closest to experiment, whereas the explicit-proton models display substantial discrepancies. On the other hand, in contrast to all explicit-proton potentials, the mW model is unable to reproduce central qualitative trends such as the anisotropy in Young's modulus and the shear modulus. This suggests that the elastic behavior of ice I$_h$ is closely related to its molecular nature, which has been coarse-grained out in the mW model. These observations are consistent with other recent manifestations concerning the limitations of the mW model in the description of mechanical properties of ice I$_h$.
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Submitted 23 November, 2018;
originally announced November 2018.