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Surface Optimization of Superconducting Aluminum Resonators for Robust Quantum Device Fabrication
Authors:
Simon J. K. Lang,
Ignaz Eisele,
Alwin Maiwald,
Emir Music,
Luis Schwarzenbach,
Carla Moran-Guizan,
Johannes Weber,
Daniela Zahn,
Thomas Mayer,
Rui N. Pereira,
Christoph Kutter
Abstract:
Aluminum (Al) remains the central material for superconducting qubits, and considerable effort has been devoted to optimizing its deposition and patterning for quantum devices. However, post-processing strategies focused on oxide removal of niobium (Nb) and tantalum (Ta) -based resonators using buffered oxide etch (BOE), which can not be used for Al. This challenge becomes particularly relevant fo…
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Aluminum (Al) remains the central material for superconducting qubits, and considerable effort has been devoted to optimizing its deposition and patterning for quantum devices. However, post-processing strategies focused on oxide removal of niobium (Nb) and tantalum (Ta) -based resonators using buffered oxide etch (BOE), which can not be used for Al. This challenge becomes particularly relevant for industry-scale fabrication with multi-chip bonding, where delays between sample preparation and cooldown require surface treatments that preserve low dielectric loss during extended exposure to ambient conditions. In this work, we investigate surface modification approaches for Al resonators subjected to a 24-hour delay prior to cryogenic measurement. Passivation using self-limiting oxygen and fluorine chemistries was evaluated utilizing different plasma processes. Remote oxygen plasma treatment reduced dielectric losses, in contrast to direct oxygen plasma. A fluorine-based plasma process was developed that passivated the Al surface for subsequent BOE treatment. However, the fluorine content in the surface resulted in higher loss, identifying fluorine as an unsuitable passivation material for Al resonators. Above all, selective oxide removal using HF (hydrogen fluoride) vapor and phosphoric acid yielded median dielectric losses as low as $\tildeδ_\mathrm{LP} = 5.7 \times 10^{-7}$ ($Q_\mathrm{LP} \approx 1.7\,\mathrm{M}$) with $\tildeδ_\mathrm{TLS} = 3.6 \times 10^{-7}$ ($Q_\mathrm{TLS} \approx 2.8\,\mathrm{M}$) in the single photon regime. Selective oxide removal provides a promising pathway for robust Al-based qubit fabrication, as it preserves low dielectric losses for a 24-hour delay before cooldown.
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Submitted 16 July, 2026; v1 submitted 7 January, 2026;
originally announced January 2026.
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Stability studies on subtractively-fabricated CMOS-compatible superconducting transmon qubits
Authors:
Chawki Dhieb,
Johannes Weber,
Samuel Taubenberger,
Carla Moran Guizan,
Simon J. K. Lang,
Zhen Luo,
Emir Music,
Alwin Maiwald,
Wilfried Lerch,
Lars Nebrich,
Marc Tornow,
Thomas Mayer,
Daniela Zahn,
Rui N. Pereira,
Christoph Kutter
Abstract:
Developing fault-tolerant quantum processors with error correction demands large arrays of physical qubits whose key performance metrics (coherence times, control fidelities) must remain within specifications over both short and long timescales. Here we investigated the temporal stability of subtractively fabricated CMOS-compatible superconducting transmon qubits. During a single cooldown and over…
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Developing fault-tolerant quantum processors with error correction demands large arrays of physical qubits whose key performance metrics (coherence times, control fidelities) must remain within specifications over both short and long timescales. Here we investigated the temporal stability of subtractively fabricated CMOS-compatible superconducting transmon qubits. During a single cooldown and over a period of 95 hours, we monitored several parameters for 8 qubits, including coherence times $T_1$ and $T_2^*$, which exhibit fluctuations originating primarily from the interaction between two-level system (TLS) defects and the host qubit. We also demonstrate that subtractively-fabricated superconducting quantum devices align with the theoretical predictions that higher mean lifetimes $T_1$ correspond to larger fluctuations. To assess long-term stability, we tracked two representative qubits over 10 cooldown cycles spanning more than one year. We observed an average total downward shift in both qubit transition frequencies of approximately 61 MHz within the thermal cycles considered. In contrast, readout resonator frequencies decreased only marginally. Meanwhile, $T_1$ exhibits fluctuations from cycle to cycle, but maintains a stable baseline value.
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Submitted 13 July, 2026; v1 submitted 19 December, 2025;
originally announced December 2025.
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CMOS-Compatible, Wafer-Scale Processed Superconducting Qubits Exceeding Energy Relaxation Times of 200us
Authors:
T. Mayer,
J. Weber,
E. Music,
C. Moran Guizan,
S. J. K. Lang,
L. Schwarzenbach,
C. Dhieb,
B. Kiliclar,
A. Maiwald,
Z. Luo,
W. Lerch,
D. Zahn,
I. Eisele,
R. N. Pereira,
C. Kutter
Abstract:
We present the results of an industry-grade fabrication of superconducting qubits on 200 mm wafers utilizing CMOS-established processing methods. By automated waferprober resistance measurements at room temperature, we demonstrate a Josephson junction fabrication yield of 99.7% (shorts and opens) across more than 10000 junctions and a qubit frequency prediction accuracy of 1.6%. In cryogenic chara…
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We present the results of an industry-grade fabrication of superconducting qubits on 200 mm wafers utilizing CMOS-established processing methods. By automated waferprober resistance measurements at room temperature, we demonstrate a Josephson junction fabrication yield of 99.7% (shorts and opens) across more than 10000 junctions and a qubit frequency prediction accuracy of 1.6%. In cryogenic characterization, we provide statistical results regarding energy relaxation times of the qubits with a median T1 of up to 100 us and individual devices consistently approaching 200 us in long-term measurements. This represents the best performance reported so far for superconducting qubits fabricated by industry-grade, wafer-level subtractive processes.
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Submitted 20 May, 2025; v1 submitted 13 May, 2025;
originally announced May 2025.
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CMOS-compatible processing and room-temperature characterization on wafer-level for scalable quantum computing
Authors:
S. J. K. Lang,
T. Mayer,
J. Weber,
C. Dhieb,
I. Eisele,
W. Lerch,
Z. Luo,
C. Moran Guizan,
E. Music,
L. Sturm-Rogon,
D. Zahn,
R. N. Pereira,
C. Kutter
Abstract:
We report on an industry-grade CMOS-compatible qubit fabrication approach using a CMOS pilot line, enabling a yield of functional devices reaching 92.8 %, with a resistance spread evaluated across the full wafer 200 mm diameter of 12.4 % and relaxation times (T1) approaching 80 us. Furthermore, we conducted a comprehensive analysis of wafer-scale room temperature (RT) characteristics collected fro…
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We report on an industry-grade CMOS-compatible qubit fabrication approach using a CMOS pilot line, enabling a yield of functional devices reaching 92.8 %, with a resistance spread evaluated across the full wafer 200 mm diameter of 12.4 % and relaxation times (T1) approaching 80 us. Furthermore, we conducted a comprehensive analysis of wafer-scale room temperature (RT) characteristics collected from multiple wafers and fabrication runs, focusing on RT measurements and their correlation to low temperature qubit parameters. From defined test structures, an across-wafer Josephson junction (JJ) area variation of 10.1 % and oxide barrier variation of 7.2 % was calculated. Additionally, from the room-temperature JJ characterization the qubit frequency can be derived on wafer-level applying the Ambegaokar-Baratoff model before low temperature measurements. This sets the stage for pre-cooldown wafer-level JJ evaluation and sorting. In particular, such early-on device characterization and validation are crucial for increasing the fabrication yield and qubit frequency targeting, which currently represent major scaling challenges. Furthermore, it enables the fabrication of large multichip quantum systems in the future. Our analysis highlight the great potential of CMOS-compatible industry-style fabrication of superconducting qubits for scalable quantum computing in a foundry pilot line cleanroom.
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Submitted 29 October, 2025; v1 submitted 25 April, 2025;
originally announced April 2025.
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Wafer-Scale Characterization of Al/AlxOy/Al Josephson Junctions at Room Temperature
Authors:
Simon J. K. Lang,
Ignaz Eisele,
Johannes Weber,
Alexandra Schewski,
Emir Music,
Alwin Maiwald,
Martin Heigl,
Daniela Zahn,
Zhen Luo,
Lars Nebrich,
Benedikt Schoof,
Thomas Mayer,
Leonhard Sturm-Rogon,
Wilfried Lerch,
Rui N. Pereira,
Christoph Kutter
Abstract:
Josephson junctions (JJs) are the key element of many devices operating at cryogenic temperatures. Development of time-efficient wafer-scale JJ characterization for process optimization and control of JJ fabrication is essential. Such statistical characterization has to rely on room temperature techniques since cryogenic measurements typically used for JJs are too time consuming and unsuitable for…
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Josephson junctions (JJs) are the key element of many devices operating at cryogenic temperatures. Development of time-efficient wafer-scale JJ characterization for process optimization and control of JJ fabrication is essential. Such statistical characterization has to rely on room temperature techniques since cryogenic measurements typically used for JJs are too time consuming and unsuitable for wafer-scale characterization. In this work, we show that from room temperature capacitance and current-voltage measurements, with proper data analysis, we can independently obtain useful parameters of the JJs on wafer-scale, like oxide thickness, tunnel coefficient, and interfacial defect densities. Moreover, based on detailed analysis of current vs voltage characteristics, different charge transport mechanisms across the junctions can be distinguished. We exemplary demonstrate the worth of these methods by studying junctions fabricated on 200 mm wafers with an industrially scale-able concept based on subtractive processing using only CMOS compatible tools. From these studies, we find that our subtractive fabrication approach yields junctions with quite homogeneous average oxide thickness across the full wafers, with a spread of less then 3$\,$%. The analysis also revealed a variation of the tunnel coefficient with oxide thickness, pointing to a stoichiometry gradient across the junctions' oxide width. Moreover, we estimated relatively low interfacial defect densities in the range of 70 - 5000$\,$defects/cm$^2$ for our junctions and established that the density increased with decreasing oxide thickness, indicating that the wet etching process applied in the JJs fabrication for oxide thickness control leads to formation of interfacial trap state
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Submitted 14 May, 2025; v1 submitted 23 April, 2025;
originally announced April 2025.