{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T03:59:58Z","timestamp":1649131198228},"reference-count":18,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Fundamentals"],"published-print":{"date-parts":[[2013]]},"DOI":"10.1587\/transfun.e96.a.2487","type":"journal-article","created":{"date-parts":[[2013,11,30]],"date-time":"2013-11-30T22:55:59Z","timestamp":1385852159000},"page":"2487-2498","source":"Crossref","is-referenced-by-count":0,"title":["Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming"],"prefix":"10.1587","volume":"E96.A","author":[{"given":"Yu","family":"ZHANG","sequence":"first","affiliation":[{"name":"University of Kitakyushu"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gong","family":"CHEN","sequence":"additional","affiliation":[{"name":"University of Kitakyushu"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bo","family":"YANG","sequence":"additional","affiliation":[{"name":"Design Algorithm Laboratory, Inc."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jing","family":"LI","sequence":"additional","affiliation":[{"name":"Design Algorithm Laboratory, Inc."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qing","family":"DONG","sequence":"additional","affiliation":[{"name":"University of Kitakyushu"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ming-Yu","family":"LI","sequence":"additional","affiliation":[{"name":"University of Kitakyushu"},{"name":"Chongqing University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shigetoshi","family":"NAKATAKE","sequence":"additional","affiliation":[{"name":"University of Kitakyushu"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] R.J. Duffin, E.L. Peterson, and C. Zener, Geometric Programming — Theory and Applications, Wiley, 1967."},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] S. Boyd, S.-J. Kim, and S. Mohan, “A tutorial on geometric programming,” Optimization and Engineering, vol.8, no.1, pp.67-127, 2007.","DOI":"10.1007\/s11081-007-9001-7"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] S. Boyd and S.-J. Kim, “Geometric programming for circuit optimization,” Proc. International Symposium on Physical Design (ISPD), p.4446, April 2005.","DOI":"10.1145\/1055137.1055148"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] M. del Mar Hershenson, S.P. Boyd, and T.H. Lee, “Optimal design of CMOS op-amp via geometric programming,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.20, no.1, pp.1-21, Jan. 2001.","DOI":"10.1109\/43.905671"},{"key":"5","unstructured":"[5] A. Debroy, R. Choudhury, and T. Sadhu, “Analysis on effective parameters influencing channel length modulation index in MOS,” International Journal of Emerging Technology and Advanced Engineering, vol.2, no.10, pp.392-398, Oct. 2012."},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] B. Liu, B. Yang, and S. Nakatake, “Layout-aware variability characterization of CMOS current sources,” IEICE Trans. Electron., vol.E95-C, no.4, pp.696-705, 2012.","DOI":"10.1587\/transele.E95.C.696"},{"key":"7","unstructured":"[7] J. Xue, Z. Ye, Y. Deng, H. Wang, L. Yang, and Z. Yu, “Layout-dependent STI stress analysis and stress-aware RF\/analog circuit design optimization,” Proc. 2009 International Conference on Computer-Aided Design, pp.521-528, ACM, 2009."},{"key":"8","unstructured":"[8] A.B. Kahng, P. Sharma, and R.O. Tapaloglu, “Exploiting STI stress for performance,” Proc. 2007 IEEE\/ACM International Conference on Computer-Aided Design, pp.83-90, Nov. 2007."},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] R.O. Topaloglu, “Standard cell and custom circuit optimization using dummy diffusions through STI width stress effect utilization,” Proc. CICC, pp.619-622, 2007.","DOI":"10.1109\/CICC.2007.4405808"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] C.-C. Wang, W. Zhao, F. Liu, M. Chen, and Y. Cao, “Modeling of layout-dependent stress effect in CMOS design,” Computer-Aided Design-Digest of Technical Papers, 2009. ICCAD 2009. IEEE\/ACM International Conference on, pp.513-520, Nov. 2009.","DOI":"10.1145\/1687399.1687496"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] Y.-M. Sheu, K.-W. Su, S. Tian, S.-J. Yang, and C.-C. Wang, “Modeling the well-edge proximity effect in highly scaled MOSFETs,” IEEE Trans. Electron Devices, vol.53, no.11, pp.2792-2798, Nov. 2006.","DOI":"10.1109\/TED.2006.884070"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] P.G. Drennan, M.L. Kniffin, and D.R. Locascio, “Implications of proximity effects for analog design,” Custom Integrated Circuits Conference, 2006, CICC'06. IEEE, pp.169-176, Sept. 2006.","DOI":"10.1109\/CICC.2006.320869"},{"key":"13","unstructured":"[13] UC Berkeley DEVICE GROUP: http:\/\/www-device.eecs.berkeley.edu"},{"key":"14","unstructured":"[14] BSIM4.5 Compact Model, www.berkeley.edu"},{"key":"15","unstructured":"[15] BSIM4.6 Compact Model, www.berkeley.edu"},{"key":"16","unstructured":"[16] GGPLAB: A simple Matlab Toolbox for Geometric Programming, www.stanford.edu\/~boyd\/ggplab"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] T.B. Hook, J. Brown, P. Cottrell, E. Adler, D. Hoyniak, J. Johnson, and R. Mann, “Lateral ion implant straggle and mask proximity effect,” IEEE Trans. Electrion Devices, vol.50, no.9, pp.1946-1951, Sept. 2003.","DOI":"10.1109\/TED.2003.815371"},{"key":"18","unstructured":"[18] CMC Website: http:\/\/www.eigroup.org\/cmc"}],"container-title":["IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E96.A\/12\/E96.A_2487\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,26]],"date-time":"2021-04-26T06:00:35Z","timestamp":1619416835000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E96.A\/12\/E96.A_2487\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"references-count":18,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2013]]}},"URL":"https:\/\/doi.org\/10.1587\/transfun.e96.a.2487","relation":{},"ISSN":["0916-8508","1745-1337"],"issn-type":[{"value":"0916-8508","type":"print"},{"value":"1745-1337","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013]]}}}